component
RT2853BHGQW
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Richtek Tech DC-DC Converters, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT2853BHGQW
Richtek Tech · DC-DC Converters · QFN-16-EP(3x3)
RT2853BHGQW from Richtek Tech, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback input voltage: connect to the midpoint of the external feedback divider to sense VOUT, placed within 5mm of the FB pin, with the IC regulating VFB at 0.765V typical. |
| 2 | VREG5 | power_out | Internal regulator output, which needs a 1µF capacitor to GND to stabilize the output voltage. |
| 3 | SS | passive | Soft-start control: an external capacitor between this pin and GND sets the soft-start time. |
| 4 | GND | power_in | Ground pin. |
| 5 | PGOOD | output | Open-drain power-good output that is pulled to PGND whenever VFB is less than 90% of its regulation threshold (typical). |
| 6 | EN | input | Enable control input: logic-high enables the converter, while logic-low forces shutdown and reduces supply current to less than 10µA; logic thresholds are 2V minimum high and 0.4V maximum low. |
| 7 | PGND | power_in | Power ground connected to the source of the internal N-channel synchronous rectifier and to the other power-ground nodes; it should be well soldered to the input and output capacitors and a large PCB area. |
| 8 | PGND | power_in | Power ground connected to the source of the internal N-channel synchronous rectifier and to the other power-ground nodes; it should be well soldered to the input and output capacitors and a large PCB area. |
| 9 | SW | output | Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI. |
| 10 | SW | output | Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI. |
| 11 | SW | output | Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI. |
| 12 | BOOT | passive | Bootstrap supply for the high-side gate driver; connect a 0.1µF capacitor between BOOT and SW. |
| 13 | VIN | power_in | Power input with an input voltage range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor. |
| 14 | VIN | power_in | Power input with an input voltage range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor. |
| 15 | VCC | power_in | Supply input for the internal linear regulator that powers the IC; connect to the input voltage and bypass to ground with a 0.1µF ceramic capacitor. |
| 16 | VS | power_in | Optional output-voltage discharge connection: an open-drain output that connects to ground when the device is disabled, and should be tied to VOUT if discharge is wanted. |
| 17 | PGND | power_in | Exposed thermal pad, listed as PGND; it should be well soldered to the input and output capacitors and a large PCB area for good power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | QFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Current | ISHDN | 1 | 10 | µA | TA = 25C, VEN = 0V | 3 | |
| Quiescent Current | IQ | 1 | 1.3 | mA | TA = 25C, VEN = 5V, VFB = 0.8V | 3 | |
| EN Voltage Logic-High | 2 | 18 | V | 3 | |||
| EN Voltage Logic-Low | 0.4 | V | 3 | ||||
| Feedback Threshold Voltage | VFB | 0.757 | 0.765 | 0.773 | V | TA = 25C | 3 |
| Feedback Threshold Voltage | VFB | 0.755 | 0.775 | V | TA = 40C to 85C | 3 | |
| Feedback Input Current | IFB | 0.01 | 0.1 | µA | VFB = 0.8V, TA = 25C | 3 | |
| VS Discharge Resistance | RDIS | 50 | 100 | Ω | VEN = 0V, VS = 0.5V | 3 | |
| VREG5 Output Voltage | VREG5 | 4.8 | 5.1 | 5.4 | V | TA = 25C, 6V ≤ VIN ≤ 18V, 0 < IVREG5 ≤ 5mA | 3 |
| VREG5 Line Regulation | 20 | mV | 6V ≤ VIN ≤ 18V, IVREG5 = 5mA | 3 | |||
| VREG5 Load Regulation | 100 | mV | 0 ≤ IVREG5 ≤ 5mA | 3 | |||
| Current Limit | ILIM | 4 | 4.5 | 6 | A | LSW = 1.4µH | 4 |
| Minimum Off-Time | tOFF(MIN) | 260 | 310 | ns | VFB = 0.7V, TA = 25C | 4 | |
| SS Charge Current | 1.4 | 2 | 2.6 | A | VSS = 0V | 4 | |
| SS Discharge Current | 0.1 | 0.2 | mA | VSS = 0.5V | 4 | ||
| UVLO Threshold Wake Up (VREG5) | 3.6 | 3.85 | 4.1 | V | 4 | ||
| UVLO Hysteresis | 0.13 | 0.35 | 0.47 | V | 4 | ||
| PGOOD Threshold (VFB Rising) | 85 | 90 | 95 | % | 4 | ||
| PGOOD Sink Current | 2.5 | 5 | mA | PGOOD = 0.5V | 4 | ||
| OVP Trip Threshold | 115 | 120 | 125 | % | 4 | ||
| UVP Trip Threshold | 65 | 70 | 75 | % | 4 | ||
| Supply Voltage, VIN, VCC | VIN, VCC | -0.3 | 21 | V | 3 | ||
| Switch Voltage, SW | SW | -0.8 | V | max printed as (VVIN + 0.3V) | 3 | ||
| Switch Voltage, SW (<10ns) | SW | -5 | 25 | V | < 10ns | 3 | |
| BOOT to SW | -0.3 | 6 | V | 3 | |||
| VREG5 to VIN or VCC | -18 | 0.3 | V | 3 | |||
| Other Pins Voltage | -0.3 | 21 | V | 3 | |||
| Power Dissipation | PD | 2.1 | W | TA = 25°C, WQFN-16L 3x3 | 3 | ||
| Junction Temperature Range (absolute maximum) | 150 | °C | 3 | ||||
| Lead Temperature (Soldering, 10 sec) | 260 | °C | Soldering, 10 sec | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 3 | |||
| Supply Voltage, VIN | VIN | 4.5 | 18 | V | 3 | ||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range | -40 | 85 | °C | 3 | |||
| Package Thermal Resistance, Junction to Ambient | θJA | 47.4 | °C/W | WQFN-16L 3x3, Note 2 | 3 | ||
| Package Thermal Resistance, Junction to Case | θJC | 7.5 | °C/W | WQFN-16L 3x3, Note 2 | 3 |
CAD (KiCad official)
- Symbol:
RT2853BHGQW - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
rt2853bhgqw-etched.step/rt2853bhgqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt2853bhgqw.step/rt2853bhgqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (23 pp, sha256
f0be9b8fcc2f1d5e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT2853BHGQW
**Richtek Tech** · DC-DC Converters · QFN-16-EP(3x3)
RT2853BHGQW from Richtek Tech, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback input voltage: connect to the midpoint of the external feedback divider to sense VOUT, placed within 5mm of the FB pin, with the IC regulating VFB at 0.765V typical. |
| 2 | VREG5 | power_out | Internal regulator output, which needs a 1µF capacitor to GND to stabilize the output voltage. |
| 3 | SS | passive | Soft-start control: an external capacitor between this pin and GND sets the soft-start time. |
| 4 | GND | power_in | Ground pin. |
| 5 | PGOOD | output | Open-drain power-good output that is pulled to PGND whenever VFB is less than 90% of its regulation threshold (typical). |
| 6 | EN | input | Enable control input: logic-high enables the converter, while logic-low forces shutdown and reduces supply current to less than 10µA; logic thresholds are 2V minimum high and 0.4V maximum low. |
| 7 | PGND | power_in | Power ground connected to the source of the internal N-channel synchronous rectifier and to the other power-ground nodes; it should be well soldered to the input and output capacitors and a large PCB area. |
| 8 | PGND | power_in | Power ground connected to the source of the internal N-channel synchronous rectifier and to the other power-ground nodes; it should be well soldered to the input and output capacitors and a large PCB area. |
| 9 | SW | output | Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI. |
| 10 | SW | output | Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI. |
| 11 | SW | output | Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI. |
| 12 | BOOT | passive | Bootstrap supply for the high-side gate driver; connect a 0.1µF capacitor between BOOT and SW. |
| 13 | VIN | power_in | Power input with an input voltage range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor. |
| 14 | VIN | power_in | Power input with an input voltage range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor. |
| 15 | VCC | power_in | Supply input for the internal linear regulator that powers the IC; connect to the input voltage and bypass to ground with a 0.1µF ceramic capacitor. |
| 16 | VS | power_in | Optional output-voltage discharge connection: an open-drain output that connects to ground when the device is disabled, and should be tied to VOUT if discharge is wanted. |
| 17 | PGND | power_in | Exposed thermal pad, listed as PGND; it should be well soldered to the input and output capacitors and a large PCB area for good power dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | QFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Current | ISHDN | | 1 | 10 | µA | TA = 25C, VEN = 0V | 3 |
| Quiescent Current | IQ | | 1 | 1.3 | mA | TA = 25C, VEN = 5V, VFB = 0.8V | 3 |
| EN Voltage Logic-High | | 2 | | 18 | V | | 3 |
| EN Voltage Logic-Low | | | | 0.4 | V | | 3 |
| Feedback Threshold Voltage | VFB | 0.757 | 0.765 | 0.773 | V | TA = 25C | 3 |
| Feedback Threshold Voltage | VFB | 0.755 | | 0.775 | V | TA = 40C to 85C | 3 |
| Feedback Input Current | IFB | | 0.01 | 0.1 | µA | VFB = 0.8V, TA = 25C | 3 |
| VS Discharge Resistance | RDIS | | 50 | 100 | Ω | VEN = 0V, VS = 0.5V | 3 |
| VREG5 Output Voltage | VREG5 | 4.8 | 5.1 | 5.4 | V | TA = 25C, 6V ≤ VIN ≤ 18V, 0 < IVREG5 ≤ 5mA | 3 |
| VREG5 Line Regulation | | | | 20 | mV | 6V ≤ VIN ≤ 18V, IVREG5 = 5mA | 3 |
| VREG5 Load Regulation | | | | 100 | mV | 0 ≤ IVREG5 ≤ 5mA | 3 |
| Current Limit | ILIM | 4 | 4.5 | 6 | A | LSW = 1.4µH | 4 |
| Minimum Off-Time | tOFF(MIN) | | 260 | 310 | ns | VFB = 0.7V, TA = 25C | 4 |
| SS Charge Current | | 1.4 | 2 | 2.6 | A | VSS = 0V | 4 |
| SS Discharge Current | | 0.1 | 0.2 | | mA | VSS = 0.5V | 4 |
| UVLO Threshold Wake Up (VREG5) | | 3.6 | 3.85 | 4.1 | V | | 4 |
| UVLO Hysteresis | | 0.13 | 0.35 | 0.47 | V | | 4 |
| PGOOD Threshold (VFB Rising) | | 85 | 90 | 95 | % | | 4 |
| PGOOD Sink Current | | 2.5 | 5 | | mA | PGOOD = 0.5V | 4 |
| OVP Trip Threshold | | 115 | 120 | 125 | % | | 4 |
| UVP Trip Threshold | | 65 | 70 | 75 | % | | 4 |
| Supply Voltage, VIN, VCC | VIN, VCC | -0.3 | | 21 | V | | 3 |
| Switch Voltage, SW | SW | -0.8 | | | V | max printed as (VVIN + 0.3V) | 3 |
| Switch Voltage, SW (<10ns) | SW | -5 | | 25 | V | < 10ns | 3 |
| BOOT to SW | | -0.3 | | 6 | V | | 3 |
| VREG5 to VIN or VCC | | -18 | | 0.3 | V | | 3 |
| Other Pins Voltage | | -0.3 | | 21 | V | | 3 |
| Power Dissipation | PD | | | 2.1 | W | TA = 25°C, WQFN-16L 3x3 | 3 |
| Junction Temperature Range (absolute maximum) | | | | 150 | °C | | 3 |
| Lead Temperature (Soldering, 10 sec) | | | | 260 | °C | Soldering, 10 sec | 3 |
| Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| ESD Susceptibility HBM | | | | 2 | kV | Human Body Model | 3 |
| Supply Voltage, VIN | VIN | 4.5 | | 18 | V | | 3 |
| Junction Temperature Range (recommended) | | -40 | | 125 | °C | | 3 |
| Ambient Temperature Range | | -40 | | 85 | °C | | 3 |
| Package Thermal Resistance, Junction to Ambient | θJA | | 47.4 | | °C/W | WQFN-16L 3x3, Note 2 | 3 |
| Package Thermal Resistance, Junction to Case | θJC | | 7.5 | | °C/W | WQFN-16L 3x3, Note 2 | 3 |
## CAD (KiCad official)
- Symbol: `RT2853BHGQW`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `rt2853bhgqw-etched.step` / `rt2853bhgqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt2853bhgqw.step` / `rt2853bhgqw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603026764826492928) (23 pp, sha256 `f0be9b8fcc2f1d5e`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt2853bhgqw-datasheet.pdf)