main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers rt2515hgsp: viewers · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
rt2515hgsp-etched.glb rt2515hgsp: factory component page (tier=lcsc) · Ray 2h ago
rt2515hgsp-etched.step rt2515hgsp: factory component page (tier=lcsc) · Ray 2h ago
rt2515hgsp-hero.glb rt2515hgsp: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
rt2515hgsp-hero.overlay.json Publish 0.1.0 · Ray 2h ago
rt2515hgsp.glb Publish 0.1.0 · Ray 2h ago
rt2515hgsp.kicad_mod Publish 0.1.0 · Ray 2h ago
rt2515hgsp.kicad_sym Publish 0.1.0 · Ray 2h ago
rt2515hgsp.lbr Publish 0.1.0 · Ray 2h ago
rt2515hgsp.step Publish 0.1.0 · Ray 2h ago

RT2515HGSP

Richtek Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8-EP

RT2515HGSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; this pin is not connected inside the device.
2 EN input Active-high chip enable; pulling this pin below 0.4V turns the regulator off, and it is enabled if left open, so connect it to VIN if not used.
3 VIN power_in Input voltage; for full-load regulation it must be between (VOUT + 0.5V) and 6V with a minimum of 1.4V, and a minimum 10µF ceramic capacitor should be placed directly at this pin.
4 NC unconnected No internal connection; this pin is not connected inside the device.
5 NC unconnected No internal connection; this pin is not connected inside the device.
6 VOUT power_out Output voltage; a minimum of 10µF capacitor should be placed directly at this pin.
7 ADJ input Feedback pin; connecting it to VOUT sets the output to 0.5V, while external feedback resistors set the output by their ratio.
8 GND power_in Ground.
9 GND power_in Exposed pad (GND); it must be soldered to a large PCB and connected to GND for maximum power dissipation.

Key specifications

Parameter Value
Manufacturer Richtek Tech
Package SOP-8-EP
Category Power Management (PMIC)
Pins 9

CAD (KiCad official)

  • Symbol: RT2515HGSP
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: rt2515hgsp-etched.step / rt2515hgsp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rt2515hgsp.step / rt2515hgsp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Richtek Tech datasheet (9 pp, sha256 a8e58d5cd3964f6e, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF