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RS74HC74XP
Public Made by Adomby adom
Jiangsu RUNIC Tech Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| rs74hc74xp-etched.step | 4d ago |
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RS74HC74XP
Jiangsu RUNIC Tech · Flip Flops · SOIC-14
RS74HC74XP from Jiangsu RUNIC Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1R̅D | input | Asynchronous reset-direct input (active LOW) that forces 1Q LOW and 1Q̅ HIGH when asserted with 1S̅D HIGH. |
| 2 | 1D | input | Data input that is stored in the flip-flop on the LOW-to-HIGH transition of 1CP when set-up and hold times are met. |
| 3 | 1CP | input | Clock input; the data at 1D is captured on its LOW-to-HIGH transition. |
| 4 | 1S̅D | input | Asynchronous set-direct input (active LOW) that forces 1Q HIGH and 1Q̅ LOW when asserted with 1R̅D HIGH. |
| 5 | 1Q | output | True flip-flop output that follows the stored data state of the first flip-flop. |
| 6 | 1Q̅ | output | Complement flip-flop output, the logic inverse of 1Q. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 2Q̅ | output | Complement flip-flop output, the logic inverse of 2Q. |
| 9 | 2Q | output | True flip-flop output that follows the stored data state of the second flip-flop. |
| 10 | 2S̅D | input | Asynchronous set-direct input (active LOW) that forces 2Q HIGH and 2Q̅ LOW when asserted with 2R̅D HIGH. |
| 11 | 2CP | input | Clock input; the data at 2D is captured on its LOW-to-HIGH transition. |
| 12 | 2D | input | Data input that is stored in the flip-flop on the LOW-to-HIGH transition of 2CP when set-up and hold times are met. |
| 13 | 2R̅D | input | Asynchronous reset-direct input (active LOW) that forces 2Q LOW and 2Q̅ HIGH when asserted with 2S̅D HIGH. |
| 14 | VCC | power_in | Supply pin; the operating supply voltage range is 1.65V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu RUNIC Tech |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 6.5 | V | 6 | ||
| Input voltage range | VI | -0.5 | 6.5 | V | 6 | ||
| Voltage range applied to any output in the high-impedance or power-off state | Vo | -0.5 | 6.5 | V | 6 | ||
| Input clamp current | IIK | -50 | mA | VI<0 | 6 | ||
| Output clamp current | IOK | -50 | mA | VO<0 | 6 | ||
| Continuous output current | IO | -50 | 50 | mA | 6 | ||
| Continuous current through VCC or GND | -100 | 100 | mA | 6 | |||
| Junction temperature | TJ | -65 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Supply voltage range | VCC | 1.65 | 5.5 | V | Operating | 7 | |
| High-level input voltage | VIH | 1.7 | V | VCC=2.3V to 2.7V | 7 | ||
| High-level input voltage | VIH | 2 | V | VCC=3V to 3.6V | 7 | ||
| Low-level input voltage | VIL | 0.7 | V | VCC=2.3V to 2.7V | 7 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC=3V to 3.6V | 7 | ||
| Input voltage | VI | 0 | 5.5 | V | 7 | ||
| High-level output current | IOH | -4 | mA | VCC=1.65V | 7 | ||
| High-level output current | IOH | -8 | mA | VCC=2.3V | 7 | ||
| High-level output current | IOH | -16 | mA | VCC=3V | 7 | ||
| High-level output current | IOH | -24 | mA | VCC=3V | 7 | ||
| High-level output current | IOH | -32 | mA | VCC=4.5V | 7 | ||
| Low-level output current | IOL | 4 | mA | VCC=1.65V | 7 | ||
| Low-level output current | IOL | 8 | mA | VCC=2.3V | 7 | ||
| Low-level output current | IOL | 16 | mA | VCC=3V | 7 | ||
| Low-level output current | IOL | 24 | mA | VCC=3V | 7 | ||
| Low-level output current | IOL | 32 | mA | VCC=4.5V | 7 | ||
| Input transition rise or fall rate | Δt/Δv | 20 | ns/V | VCC=1.8V±0.15V, 2.5V±0.2V | 7 | ||
| Input transition rise or fall rate | Δt/Δv | 10 | ns/V | VCC=3.3V±0.3V | 7 | ||
| Operating temperature | TA | -40 | 125 | °C | 7 | ||
| Package thermal impedance SOIC-14(SOP14) | θJA | 105 | °C/W | SOIC-14(SOP14), calculated per JESD-51 | 6 | ||
| High-level output voltage | VOH | 1.2 | V | IOH = -4mA, 1.65V | 8 | ||
| High-level output voltage | VOH | 1.9 | V | IOH = -8mA, 2.3V | 8 | ||
| High-level output voltage | VOH | 2.4 | V | IOH = -16mA, 3V | 8 | ||
| High-level output voltage | VOH | 2.3 | V | IOH = -24mA, 3V | 8 | ||
| High-level output voltage | VOH | 3.8 | V | IOH = -32mA, 4.5V | 8 | ||
| Low-level output voltage | VOL | 0.1 | V | IOL = 100μA, 1.65V to 5.5V, Full | 8 | ||
| Low-level output voltage | VOL | 0.45 | V | IOL = 4mA, 1.65V | 8 | ||
| Low-level output voltage | VOL | 0.3 | V | IOL = 8mA, 2.3V | 8 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 16mA, 3V | 8 | ||
| Low-level output voltage | VOL | 0.55 | V | IOL = 24mA, 3V | 8 | ||
| Input leakage current | II | -1 | 0.1 | 1 | µA | All inputs VI=5.5V or GND, 0V to 5.5V, +25C | 8 |
| Input leakage current | II | -5 | 5 | µA | All inputs VI=5.5V or GND, 0V to 5.5V, Full | 8 | |
| Power-off leakage current | Ioff | -1 | 0.1 | 1 | µA | VI or VO=5.5V, VCC=0, +25C | 8 |
| Power-off leakage current | Ioff | -10 | 10 | µA | VI or VO=5.5V, VCC=0, Full | 8 | |
| Quiescent supply current | ICC | 0.1 | 1 | µA | VI=5.5V or GND, IO=0, 1.65V to 5.5V, +25C | 8 | |
| Quiescent supply current | ICC | 10 | µA | VI=5.5V or GND, IO=0, 1.65V to 5.5V, Full | 8 | ||
| Additional quiescent supply current | ΔICC | 500 | µA | One input at VCC-0.6V, other inputs at VCC or GND, 3V to 5.5V, Full | 8 | ||
| Maximum clock frequency | fmax | 30 | MHz | -40°C to 85°C, VCC=1.8V | 9 | ||
| Maximum clock frequency | fmax | 65 | MHz | -40°C to 85°C, VCC=2.5V | 9 | ||
| Maximum clock frequency | fmax | 100 | MHz | -40°C to 85°C, VCC=3.3V | 9 | ||
| Maximum clock frequency | fmax | 155 | MHz | -40°C to 85°C, VCC=5V | 9 | ||
| Propagation delay nCP to nQ | tpd | 4.8 | 23.5 | ns | -40°C to 85°C, VCC=1.8V | 9 | |
| Propagation delay nCP to nQ | tpd | 2.2 | 15.5 | ns | -40°C to 85°C, VCC=2.5V | 9 | |
| Propagation delay nCP to nQ | tpd | 2.2 | 11.5 | ns | -40°C to 85°C, VCC=3.3V | 9 | |
| Propagation delay nCP to nQ | tpd | 1.4 | 9.2 | ns | -40°C to 85°C, VCC=5V | 9 | |
| Propagation delay nSD or nRD to nQ or nQ̅ | tpd | 4.4 | 27 | ns | -40°C to 85°C, VCC=1.8V | 9 | |
| Propagation delay nSD or nRD to nQ or nQ̅ | tpd | 2.3 | 16 | ns | -40°C to 85°C, VCC=2.5V | 9 | |
| Propagation delay nSD or nRD to nQ or nQ̅ | tpd | 1.7 | 12 | ns | -40°C to 85°C, VCC=3.3V | 9 | |
| Propagation delay nSD or nRD to nQ or nQ̅ | tpd | 1.6 | 9.4 | ns | -40°C to 85°C, VCC=5V | 9 |
CAD (KiCad official)
- Symbol:
RS74HC74XP - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
rs74hc74xp-etched.step/rs74hc74xp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rs74hc74xp.step/rs74hc74xp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Jiangsu RUNIC Tech datasheet (15 pp, sha256
fff9f54fcb3a091d, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).