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docs rs6g07xp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers rs6g07xp: viewers · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
page.json rs6g07xp: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 18h ago
README.md rs6g07xp: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago
rs6g07xp-etched.fit.json rs6g07xp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
rs6g07xp-etched.glb rs6g07xp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
rs6g07xp-etched.step rs6g07xp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
rs6g07xp.glb Publish 0.1.0 · Ray 1mo ago
rs6g07xp.kicad_mod Publish 0.1.0 · Ray 1mo ago
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rs6g07xp.step Publish 0.1.0 · Ray 1mo ago

RS6G07XP

Jiangsu RUNIC Tech · Buffer/Driver/Transceiver · SOIC-14

RS6G07XP from Jiangsu RUNIC Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 buffer input. CMOS logic input, 5.5V tolerant regardless of VCC. When A=L output Y=L; when A=H output Y=Hi-Z (open drain).
2 1Y output Channel 1 open-drain buffer output. Tolerant to 5.5V independent of VCC. Requires external pull-up; sinks up to ±24 mA at VCC=3.0 V.
3 2A input Channel 2 buffer input. CMOS logic input, 5.5V tolerant regardless of VCC.
4 2Y output Channel 2 open-drain buffer output. Tolerant to 5.5V independent of VCC. Requires external pull-up.
5 3A input Channel 3 buffer input. CMOS logic input, 5.5V tolerant regardless of VCC.
6 3Y output Channel 3 open-drain buffer output. Tolerant to 5.5V independent of VCC. Requires external pull-up.
7 GND power_in Ground reference (0 V) for the device.
8 4Y output Channel 4 open-drain buffer output. Tolerant to 5.5V independent of VCC. Requires external pull-up.
9 4A input Channel 4 buffer input. CMOS logic input, 5.5V tolerant regardless of VCC.
10 5Y output Channel 5 open-drain buffer output. Tolerant to 5.5V independent of VCC. Requires external pull-up.
11 5A input Channel 5 buffer input. CMOS logic input, 5.5V tolerant regardless of VCC.
12 6Y output Channel 6 open-drain buffer output. Tolerant to 5.5V independent of VCC. Requires external pull-up.
13 6A input Channel 6 buffer input. CMOS logic input, 5.5V tolerant regardless of VCC.
14 VCC power_in Positive supply input. Recommended operating range 1.65 V to 5.5 V (data retention down to 1.5 V). Absolute max 6.5 V.

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • RS6G07XP
  • RS6G07XPXQ

CAD (KiCad official)

  • Symbol: RS6G07XP
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: rs6g07xp-etched.step / rs6g07xp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs6g07xp.step / rs6g07xp.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
rs6g07xp.step 195 KB You want the bare part, or you mark your own boards.
rs6g07xp-etched.step 2.3 MB You want the part with RS6G07XP already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 554 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (10 pp, sha256 8471a0d4d1126504, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF