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Contents

README

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RS40N120T

REASUNOS · MOSFETs · TO-220

RS40N120T from REASUNOS, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; controls the channel, with a VGS rating of ±20 V and a gate threshold of 1.0 to 2.5 V at ID=250µA.
2 D passive Drain, also connected to the mounting tab; VDSS is 40 V and continuous drain current is 120 A at TC=25℃.
3 S passive Source; continuous source current is 120 A through the integral pn diode, with VSD up to 1.2 V at IS=15A.

Key specifications

Parameter Value
Manufacturer REASUNOS
Package TO-220
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-to-Source Breakdown Voltage BVDSS 40 V VGS=0V,ID=250µA 2
Drain-to-Source Leakage Current IDSS 1 µA VDS=40V,VGS=0V 2
Gate-to-Source Forward Leakage IGSS 100 nA VGS=20V,VDS=0V 2
Gate-to-Source Reverse Leakage IGSS -100 nA VGS=-20V,VDS=0V 2
Static Drain-to-Source On-Resistance RDS(on) 2.8 3.5 mΩ VGS=10V,ID=15A 2
Static Drain-to-Source On-Resistance RDS(on) 4 4.8 mΩ VGS=4.5V,ID=10A 2
Gate Threshold Voltage VGS(TH) 1 2.5 V VGS=VDS,ID=250µA 2
Continuous Source Current IS 120 A Integral pn-diode in MOSFET 3
Maximum Pulsed Current ISM 390 A Integral pn-diode in MOSFET 3
Diode Forward Voltage VSD 1.2 V IS=15A,VGS=0V 3
Drain-to-Source Voltage VDSS 40 V Tc=25℃ 1
Continuous Drain Current ID 120 A TC=25℃ 1
Continuous Drain Current ID 76 A TC=100℃ 1
Pulsed Drain Current IDM 390 A 1
Power Dissipation PD 110 W Tc=25℃ 1
Gate-to-Source Voltage VGS -20 20 V 1
Single Pulse Avalanche Energy EAS 272 mJ L = 0.5mH,VDD = 40V, VG = 10V, Tj = 25℃ 1
Maximum Soldering Temperature, Leads TL 300 ℃ Leads at 0.063in(1.6mm) from Case for 10 seconds 1
Maximum Soldering Temperature, Package Body TPKG 260 ℃ Package Body for 10 seconds 1
Operating Junction and Storage Temperature Range TJ, TSTG -55 150 ℃ 1
Junction-to-Case Thermal Resistance RθJC 1.14 ℃/W Drain lead soldered to water cooled heatsink, PD adjusted for a peak junction temperature of +150℃ 2
Junction-to-Ambient Thermal Resistance RθJA 20 ℃/W 1 cubic foot chamber, free air 2
Turn-on Delay Time td(ON) 12 nS VDS=20V ID=20A RG=25Ω VGS=10V 2
Rise Time trise 54 nS VDS=20V ID=20A RG=25Ω VGS=10V 2
Turn-OFF Delay Time td(OFF) 120 nS VDS=20V ID=20A RG=25Ω VGS=10V 2
Fall Time tfall 80 nS VDS=20V ID=20A RG=25Ω VGS=10V 2
Input Capacitance Ciss 4645 pF VGS=0V, VDS=20V, f=1.0MHz 3
Output Capacitance Coss 436 pF VGS=0V, VDS=20V, f=1.0MHz 3
Reverse Transfer Capacitance Crss 360 pF VGS=0V, VDS=20V, f=1.0MHz 3
Total Gate Charge Qg 102 nC VDS=20V, ID=20A, VGS=10V 3
Total Gate Charge (second row) Qg 49 nC VDS=20V, ID=20A, VGS=10V 3
Gate-to-Source Charge Qgs 15.8 nC VDS=20V, ID=20A, VGS=10V 3
Gate-to-Drain (Miller) Charge Qgd 21.9 nC VDS=20V, ID=20A, VGS=10V 3
Reverse Recovery Time trr 22.3 nS VGS=0V, IS=20A, di/dt=100A/µs 3
Reverse Recovery Charge Qrr 7.4 nC VGS=0V, IS=20A, di/dt=100A/µs 3

CAD (KiCad official)

  • Symbol: RS40N120T
  • Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
  • 3D model: TO-220 (KiCad packages3D, STEP)
  • 3D model files: rs40n120t-etched.step / rs40n120t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs40n120t.step / rs40n120t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: REASUNOS datasheet (9 pp, sha256 efbe63edbbb2b1ef, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF