component
RS3217-3.3XF5
Public Made by Adomby adom
Jiangsu RUNIC Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RS3217-3.3XF5
Jiangsu RUNIC Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
RS3217-3.3XF5 from Jiangsu RUNIC Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input voltage supply that must be closely decoupled to GND with a 1µF or greater capacitor. |
| 2 | GND | power_in | Common ground for the device. |
| 3 | EN | input | Enable input: a voltage below VIL turns the regulator off and discharges the output to GND through an internal pulldown resistor, a voltage above VIH enables the output, and the pin must not be left floating (it can be tied to IN if unused). |
| 4 | NC | unconnected | Not internally connected. |
| 5 | OUT | power_out | Regulated output voltage that requires a minimum 1µF low-ESR capacitor connected to this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu RUNIC Tech |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range on IN | VIN | 1.9 | 5.5 | V | 7 | ||
| Output Voltage Range on OUT | VOUT | 1.2 | 4.5 | V | 7 | ||
| Input Voltage Range on EN | VEN | 0 | 5.5 | V | 7 | ||
| Output Current Range on IOUT | IOUT | 0 | 500 | mA | 7 | ||
| Operating Ambient Temperature Range | TA | -40 | 125 | °C | 7 | ||
| Input voltage | VIN | -0.3 | 6 | V | 7 | ||
| Enable input voltage | VEN | -0.3 | 6 | V | 7 | ||
| Output voltage | VOUT | -0.3 | V | 7 | |||
| Package thermal impedance, SOT23-5 | θJA | 200 | °C/W | SOT23-5, JESD-51, packages soldered to PCB | 7 | ||
| Junction temperature | TJ | -40 | 125 | °C | 7 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| Load Temperature (Soldering, 10sec) | 260 | °C | Soldering, 10 sec | 7 | |||
| Input Voltage | VIN | 1.9 | 5.5 | V | 8 | ||
| Quiescent Current | IQ | 16 | 25 | μA | VEN=1.2V, IOUT=0mA | 8 | |
| Shutdown Current | ISD | 0.01 | 1 | μA | VEN = 0V | 8 | |
| Output Voltage Range | VOUT | 1.2 | 4.5 | V | 8 | ||
| DC Output Accuracy, TJ = 25°C | ΔVOUT | -1.5 | 1.5 | % | TJ = 25°C | 8 | |
| Line Regulation | ΔVOUT(ΔVIN) | 0.005 | 0.05 | %/V | VIN=2.8 to 5.5V, IOUT=1mA | 8 | |
| Load Regulation | ΔVOUT(ΔIOUT) | 3 | 6 | mV | IOUT=1mA to 500mA | 8 | |
| Maximum output current | IOUTMAX | 500 | mA | 8 | |||
| Output discharge FET Rdson | RDIS | 40 | 70 | 90 | Ω | VEN<VIL (output disable), VIN=2.8V | 8 |
| Dropout Voltage | VDO | 220 | 255 | mV | IOUT=500mA, VOUT=3.3V | 8 | |
| EN Input leakage current (VEN = 0V) | IEN | 0.001 | 0.1 | μA | VIN=5.5, VEN = 0V | 9 | |
| EN Input leakage current (VEN = 5.5V) | IEN | 0.4 | 1 | μA | VIN=5.5, VEN = 5.5V | 9 | |
| Output Turn-on Delay Time | TON | 60 | 150 | μs | From VEN> VIH to VOUT = 95% of VOUT(NOM) | 9 | |
| Over Current Limit | ILMT | 600 | 1100 | 1300 | mA | 9 | |
| Short Current Limit | ISHORT | 25 | 55 | 100 | mA | VOUT=0V | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO component connections is str | 17 |
CAD (KiCad official)
- Symbol:
RS3217-3.3XF5 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
rs3217-3-3xf5-etched.step/rs3217-3-3xf5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rs3217-3-3xf5.step/rs3217-3-3xf5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Jiangsu RUNIC Tech datasheet (21 pp, sha256
92fca912e379010f, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RS3217-3.3XF5
**Jiangsu RUNIC Tech** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
RS3217-3.3XF5 from Jiangsu RUNIC Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input voltage supply that must be closely decoupled to GND with a 1µF or greater capacitor. |
| 2 | GND | power_in | Common ground for the device. |
| 3 | EN | input | Enable input: a voltage below VIL turns the regulator off and discharges the output to GND through an internal pulldown resistor, a voltage above VIH enables the output, and the pin must not be left floating (it can be tied to IN if unused). |
| 4 | NC | unconnected | Not internally connected. |
| 5 | OUT | power_out | Regulated output voltage that requires a minimum 1µF low-ESR capacitor connected to this pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu RUNIC Tech |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range on IN | VIN | 1.9 | | 5.5 | V | | 7 |
| Output Voltage Range on OUT | VOUT | 1.2 | | 4.5 | V | | 7 |
| Input Voltage Range on EN | VEN | 0 | | 5.5 | V | | 7 |
| Output Current Range on IOUT | IOUT | 0 | | 500 | mA | | 7 |
| Operating Ambient Temperature Range | TA | -40 | | 125 | °C | | 7 |
| Input voltage | VIN | -0.3 | | 6 | V | | 7 |
| Enable input voltage | VEN | -0.3 | | 6 | V | | 7 |
| Output voltage | VOUT | -0.3 | | | V | | 7 |
| Package thermal impedance, SOT23-5 | θJA | | | 200 | °C/W | SOT23-5, JESD-51, packages soldered to PCB | 7 |
| Junction temperature | TJ | -40 | | 125 | °C | | 7 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 7 |
| Load Temperature (Soldering, 10sec) | | | | 260 | °C | Soldering, 10 sec | 7 |
| Input Voltage | VIN | 1.9 | | 5.5 | V | | 8 |
| Quiescent Current | IQ | | 16 | 25 | μA | VEN=1.2V, IOUT=0mA | 8 |
| Shutdown Current | ISD | | 0.01 | 1 | μA | VEN = 0V | 8 |
| Output Voltage Range | VOUT | 1.2 | | 4.5 | V | | 8 |
| DC Output Accuracy, TJ = 25°C | ΔVOUT | -1.5 | | 1.5 | % | TJ = 25°C | 8 |
| Line Regulation | ΔVOUT(ΔVIN) | | 0.005 | 0.05 | %/V | VIN=2.8 to 5.5V, IOUT=1mA | 8 |
| Load Regulation | ΔVOUT(ΔIOUT) | | 3 | 6 | mV | IOUT=1mA to 500mA | 8 |
| Maximum output current | IOUTMAX | | | 500 | mA | | 8 |
| Output discharge FET Rdson | RDIS | 40 | 70 | 90 | Ω | VEN<VIL (output disable), VIN=2.8V | 8 |
| Dropout Voltage | VDO | | 220 | 255 | mV | IOUT=500mA, VOUT=3.3V | 8 |
| EN Input leakage current (VEN = 0V) | IEN | | 0.001 | 0.1 | μA | VIN=5.5, VEN = 0V | 9 |
| EN Input leakage current (VEN = 5.5V) | IEN | | 0.4 | 1 | μA | VIN=5.5, VEN = 5.5V | 9 |
| Output Turn-on Delay Time | TON | | 60 | 150 | μs | From VEN> VIH to VOUT = 95% of VOUT(NOM) | 9 |
| Over Current Limit | ILMT | 600 | 1100 | 1300 | mA | | 9 |
| Short Current Limit | ISHORT | 25 | 55 | 100 | mA | VOUT=0V | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO component connections is str | 17 |
## CAD (KiCad official)
- Symbol: `RS3217-3.3XF5`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `rs3217-3-3xf5-etched.step` / `rs3217-3-3xf5-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rs3217-3-3xf5.step` / `rs3217-3-3xf5.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Jiangsu RUNIC Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604443773929730048) (21 pp, sha256 `92fca912e379010f`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rs3217-3-3xf5-datasheet.pdf)