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RS240XS20

Public Made by Adom

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Jiangsu RUNIC Tech Buffers, Drivers, Receivers, Transceivers, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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RS240XS20

Jiangsu RUNIC Tech · Buffers, Drivers, Receivers, Transceivers · SOP-20

RS240XS20 from Jiangsu RUNIC Tech, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for the 1Y outputs; pulling it high places all 1Y outputs in 3-state mode.
2 1A0 input Data input to the first channel of the 1A buffer group; logic levels follow the recommended VIH/VIL limits.
3 2Y0 output Buffered output of the 2A0 channel, which enters the high-impedance state when 2OE is high.
4 1A1 input Data input to the second channel of the 1A buffer group; logic levels follow the recommended VIH/VIL limits.
5 2Y1 output Buffered output of the 2A1 channel, which enters the high-impedance state when 2OE is high.
6 1A2 input Data input to the third channel of the 1A buffer group; logic levels follow the recommended VIH/VIL limits.
7 2Y2 output Buffered output of the 2A2 channel, which enters the high-impedance state when 2OE is high.
8 1A3 input Data input to the fourth channel of the 1A buffer group; logic levels follow the recommended VIH/VIL limits.
9 2Y3 output Buffered output of the 2A3 channel, which enters the high-impedance state when 2OE is high.
10 GND power_in Ground reference for the device.
11 2A3 input Data input to the fourth channel of the 2A buffer group; logic levels follow the recommended VIH/VIL limits.
12 1Y3 output Buffered output of the 1A3 channel, which enters the high-impedance state when 1OE is high.
13 2A2 input Data input to the third channel of the 2A buffer group; logic levels follow the recommended VIH/VIL limits.
14 1Y2 output Buffered output of the 1A2 channel, which enters the high-impedance state when 1OE is high.
15 2A1 input Data input to the second channel of the 2A buffer group; logic levels follow the recommended VIH/VIL limits.
16 1Y1 output Buffered output of the 1A1 channel, which enters the high-impedance state when 1OE is high.
17 2A0 input Data input to the first channel of the 2A buffer group; logic levels follow the recommended VIH/VIL limits.
18 1Y0 output Buffered output of the 1A0 channel, which enters the high-impedance state when 1OE is high.
19 2OE input Active-low output enable for the 2Y outputs; pulling it high places all 2Y outputs in 3-state mode.
20 VCC power_in Supply voltage, 1.65V to 5.5V.

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package SOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 6.5 V 7
Input voltage range VI -0.5 6.5 V 7
Output voltage range VO -0.5 V max printed as VCC+0.5 7
Input clamp current IIK -50 mA VI<0 7
Output clamp current IOK -50 mA Vo<0 7
Continuous output current IO -50 50 mA 7
Continuous current through VCC or GND -100 100 mA 7
Package thermal impedance SOP20 θJA 40 °C/W SOP20 package 7
Junction temperature TJ -40 150 °C 7
Storage temperature Tstg -65 150 °C 7
Supply voltage VCC 1.65 5.5 V 8
High-level input voltage VIH 1.7 V VCC 2.3V to 2.7V 8
High-level input voltage VIH 2 V VCC 3V to 3.6V 8
Low-level input voltage VIL 0.7 V VCC 2.3V to 2.7V 8
Low-level input voltage VIL 0.8 V VCC 3V to 3.6V 8
Input voltage VI 0 5.5 V 8
Output voltage VO 0 V max is VCC 8
High-level output current IOH -4 mA VCC 1.65V to 1.95V 8
High-level output current IOH -8 mA VCC 2.3V to 2.7V 8
High-level output current IOH -24 mA VCC 3V to 3.6V 8
High-level output current IOH -32 mA VCC 4.5V to 5.5V 8
Low-level output current IOL 4 mA VCC 1.65V to 1.95V 8
Low-level output current IOL 8 mA VCC 2.3V to 2.7V 8
Low-level output current IOL 24 mA VCC 3V to 3.6V 8
Low-level output current IOL 32 mA VCC 4.5V to 5.5V 8
Input transition rise or fall rate Δt/Δv 20 ns/V Data inputs, VCC 1.65V to 1.95V 8
Input transition rise or fall rate Δt/Δv 10 ns/V Data inputs, VCC 3V to 3.6V 8
Input transition rise or fall rate Δt/Δv 5 ns/V Data inputs, VCC 4.5V to 5.5V 8
Operating free-air temperature TA -40 125 °C 8
High-level output voltage VOH 1.2 V IOH = -4mA, VI =VIH, VCC 1.65V 9
High-level output voltage VOH 1.9 V IOH = -8mA, VI =VIH, VCC 2.3V 9
High-level output voltage VOH 2.4 V IOH = -24mA, VI =VIH, VCC 3V 9
High-level output voltage VOH 3.8 V IOH = -32mA, VI =VIH, VCC 4.5V 9
Low-level output voltage VOL 0.1 V IOL = 100 µA, VI =VIL, VCC 1.65V to 4.5V 9
Low-level output voltage VOL 0.45 V IOL = 4mA, VI =VIL, VCC 1.65V 9
Low-level output voltage VOL 0.3 V IOL = 8mA, VI =VIL, VCC 2.3V 9
Low-level output voltage VOL 0.55 V IOL = 24mA, VI =VIL, VCC 3V 9
Input current II -1 1 µA VI = 5.5V or GND, VCC 5.5V, +25C 9
Off-state input/output current Ioff -1 1 µA VI or VO= 0 to 5.5V, VCC 0V, +25C 9
Off-state input/output current Ioff -2 2 µA VI or VO= 0 to 5.5V, VCC 0V, Full 9
High-impedance output current IOZ -1 1 µA VO = VCC or GND, OE=VIH, VCC 1.65V to 5.5V, +25C 9
High-impedance output current IOZ -2 2 µA VO = VCC or GND, OE=VIH, VCC 1.65V to 5.5V, Full 9
VCC supply current ICC 1 µA VI = VCC or GND, IO = 0, VCC 1.65V to 5.5V, +25C 9
VCC supply current ICC 5 µA VI = VCC or GND, IO = 0, VCC 1.65V to 5.5V, Full 9
VCC supply current ICC -2 µA VI = VCC or GND, IO = 0, VCC 0V, Full 9
Additional supply current per input ΔICC 50 µA One A port at VCC, 0.6V, Y port = open, VCC 3V to 5.5V, Full 9
Input capacitance CI 8.5 pF VI = VCC or GND, VCC 3.3V, +25C 9
Output capacitance CO 8.5 pF VO = VCC or GND, VCC 3.3V, +25C 9
Propagation delay An to Yn tPLH/tPHL 1.4 21.7 ns VCC=1.8V ±0.15V 10
Propagation delay An to Yn tPLH/tPHL 1 9.1 ns VCC=2.5V ±0.2V 10
Propagation delay An to Yn tPLH/tPHL 0.7 7.8 ns VCC=3.3V ±0.3V 10
Propagation delay An to Yn tPLH/tPHL 0.5 7.5 ns VCC=5V ±0.5V 10
Disable time OE to Yn tPHZ/tPLZ 2 32.5 ns VCC=1.8V ±0.15V 10
Disable time OE to Yn tPHZ/tPLZ 1.5 13.3 ns VCC=2.5V ±0.2V 10
Disable time OE to Yn tPHZ/tPLZ 1.3 12.3 ns VCC=3.3V ±0.3V 10
Disable time OE to Yn tPHZ/tPLZ 1.2 10.5 ns VCC=5V ±0.5V 10

CAD (KiCad official)

  • Symbol: RS240XS20
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20 (KiCad packages3D, STEP)
  • 3D model files: rs240xs20-etched.step / rs240xs20-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs240xs20.step / rs240xs20.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (16 pp, sha256 7bab3cfafc3e862e, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF