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RS240TXS20
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Jiangsu RUNIC Tech Buffers, Drivers, Receivers, Transceivers, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RS240TXS20
Jiangsu RUNIC Tech · Buffers, Drivers, Receivers, Transceivers · SOP-20
RS240TXS20 from Jiangsu RUNIC Tech, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for the first 4-bit buffer; pulling 1OE high places all first-buffer outputs (1Y0-1Y3) in the 3-state mode. |
| 2 | 1A0 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A0 appears on 1Y0, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 3 | 2Y0 | output | Output of the second buffer; it presents the inverted 2A0 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 4 | 1A1 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A1 appears on 1Y1, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 5 | 2Y1 | output | Output of the second buffer; it presents the inverted 2A1 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 6 | 1A2 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A2 appears on 1Y2, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 7 | 2Y2 | output | Output of the second buffer; it presents the inverted 2A2 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 8 | 1A3 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A3 appears on 1Y3, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 9 | 2Y3 | output | Output of the second buffer; it presents the inverted 2A3 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | 2A3 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A3 appears on 2Y3, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 12 | 1Y3 | output | Output of the first buffer; it presents the inverted 1A3 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 13 | 2A2 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A2 appears on 2Y2, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 14 | 1Y2 | output | Output of the first buffer; it presents the inverted 1A2 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 15 | 2A1 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A1 appears on 2Y1, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 16 | 1Y1 | output | Output of the first buffer; it presents the inverted 1A1 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 17 | 2A0 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A0 appears on 2Y0, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 18 | 1Y0 | output | Output of the first buffer; it presents the inverted 1A0 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 19 | 2OE | input | Active-low output enable for the second 4-bit buffer; pulling 2OE high places all second-buffer outputs (2Y0-2Y3) in the 3-state mode. |
| 20 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V (4.5 V ≤ VCC ≤ 5.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu RUNIC Tech |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5.5 | V | 8 | ||
| High-level input voltage | VIH | 2 | V | VCC=4.5V to 5.5V | 8 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC=4.5V to 5.5V | 8 | ||
| Input voltage | VI | 0 | V | 8 | |||
| Output voltage | VO | 0 | V | 8 | |||
| High-level output current | IOH | -24 | mA | VCC=4.5V to 5.5V | 8 | ||
| Low-level output current | IOL | 24 | mA | VCC=4.5V to 5.5V | 8 | ||
| Input transition rise or fall rate | Δt/Δv | 8 | ns/V | VCC=4.5V to 5.5V | 8 | ||
| Operating free-air temperature | TA | -40 | 125 | °C | 8 | ||
| Supply voltage range | VCC | -0.5 | 6.5 | V | 7 | ||
| Input voltage range | VI | -0.5 | 6.5 | V | 7 | ||
| Output voltage range | VO | -0.5 | V | 7 | |||
| Input clamp current | IIK | -50 | mA | VI<0 | 7 | ||
| Output clamp current | IOK | -50 | mA | Vo<0 | 7 | ||
| Continuous output current | IO | -50 | 50 | mA | 7 | ||
| Continuous current through VCC or GND | -100 | 100 | mA | 7 | |||
| Junction temperature | TJ | -40 | 150 | °C | 7 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| Package thermal impedance, SOP20 | θJA | 40 | °C/W | SOP20 package, calculated per JESD-51 | 7 | ||
| Output high voltage, 50 µA | VOH | 4.4 | V | IOH = -50µA; VCC=4.5V; Full | 8 | ||
| Output high voltage, 50 µA | VOH | 5.4 | V | IOH = -50µA; VCC=5.5V; Full | 8 | ||
| Output high voltage, 24 mA | VOH | 3.76 | V | IOH = -24mA; VCC=4.5V | 8 | ||
| Output high voltage, 24 mA | VOH | 4.76 | V | IOH = -24mA; VCC=5.5V | 8 | ||
| Output high voltage, 50 mA | VOH | 3.85 | V | IOH = -50mA; VCC=5.5V | 8 | ||
| Output low voltage, 50 µA | VOL | 0.1 | V | IOL = 50µA; VCC=4.5V | 8 | ||
| Output low voltage, 24 mA | VOL | 0.73 | V | IOL = 24mA; VCC=4.5V | 8 | ||
| Output low voltage, 24 mA | VOL | 0.69 | V | IOL = 24mA; VCC=5.5V | 8 | ||
| Output low voltage, 50 mA | VOL | 1.65 | V | IOL = 50mA; VCC=5.5V | 8 | ||
| Input current | II | -1 | 1 | µA | VI = VCC or GND; VCC 5.5V; +25C | 8 | |
| Input current | II | -2 | 2 | µA | VI = VCC or GND; VCC 5.5V; Full | 8 | |
| Power-off leakage current | Ioff | -1 | 1 | µA | VI or VO= 0 to 5.5V; VCC 0V; +25C | 8 | |
| Power-off leakage current | Ioff | -2 | 2 | µA | VI or VO= 0 to 5.5V; VCC 0V; Full | 8 | |
| Off-state (high-impedance) output current | IOZ | -1 | 1 | µA | VO = VCC or GND, VI = VIH or VIL; VCC 5.5V; +25C | 8 | |
| Off-state (high-impedance) output current | IOZ | -2.5 | 2.5 | µA | VO = VCC or GND, VI = VIH or VIL; VCC 5.5V; Full | 8 | |
| Quiescent supply current | ICC | 40 | µA | VI = VCC or GND; IO = 0; VCC 5.5V; Full | 8 | ||
| Additional supply current per input | ΔICC | 1.5 | mA | One input at 3.4 V, Other inputs at GND or VCC; VCC 5.5V; Full | 8 | ||
| Propagation delay tPLH, An to Yn | tPLH | 2.3 | 5 | 8 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Propagation delay tPLH, An to Yn | tPLH | 2.2 | 9.2 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 | |
| Propagation delay tPHL, An to Yn | tPHL | 2.2 | 4.9 | 7.9 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Propagation delay tPHL, An to Yn | tPHL | 2.1 | 8.9 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 | |
| Disable time tPHZ, OE to Yn | tPHZ | 1.9 | 4.5 | 7.7 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Disable time tPHZ, OE to Yn | tPHZ | 1.8 | 8.3 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 | |
| Disable time tPLZ, OE to Yn | tPLZ | 2.4 | 5.3 | 8.3 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Disable time tPLZ, OE to Yn | tPLZ | 2.2 | 9.8 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 | |
| Enable time tPZH, OE to Yn | tPZH | 2.8 | 6.3 | 11.9 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Enable time tPZH, OE to Yn | tPZH | 1.8 | 12.9 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 | |
| Enable time tPZL, OE to Yn | tPZL | 1.2 | 3.3 | 5.6 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Enable time tPZL, OE to Yn | tPZL | 0.9 | 9.4 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
CAD (KiCad official)
- Symbol:
RS240TXS20 - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
rs240txs20-etched.step/rs240txs20-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rs240txs20.step/rs240txs20.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Jiangsu RUNIC Tech datasheet (15 pp, sha256
7ca59235985e3ec5, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RS240TXS20
**Jiangsu RUNIC Tech** · Buffers, Drivers, Receivers, Transceivers · SOP-20
RS240TXS20 from Jiangsu RUNIC Tech, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for the first 4-bit buffer; pulling 1OE high places all first-buffer outputs (1Y0-1Y3) in the 3-state mode. |
| 2 | 1A0 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A0 appears on 1Y0, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 3 | 2Y0 | output | Output of the second buffer; it presents the inverted 2A0 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 4 | 1A1 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A1 appears on 1Y1, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 5 | 2Y1 | output | Output of the second buffer; it presents the inverted 2A1 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 6 | 1A2 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A2 appears on 1Y2, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 7 | 2Y2 | output | Output of the second buffer; it presents the inverted 2A2 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 8 | 1A3 | input | Data input of the first buffer; when 1OE is low the inverted value of 1A3 appears on 1Y3, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 9 | 2Y3 | output | Output of the second buffer; it presents the inverted 2A3 data when 2OE is low and goes high-impedance when 2OE is high, with ±24 mA drive at 5 V. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | 2A3 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A3 appears on 2Y3, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 12 | 1Y3 | output | Output of the first buffer; it presents the inverted 1A3 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 13 | 2A2 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A2 appears on 2Y2, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 14 | 1Y2 | output | Output of the first buffer; it presents the inverted 1A2 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 15 | 2A1 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A1 appears on 2Y1, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 16 | 1Y1 | output | Output of the first buffer; it presents the inverted 1A1 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 17 | 2A0 | input | Data input of the second buffer; when 2OE is low the inverted value of 2A0 appears on 2Y0, and it is TTL-compatible (VIH min 2 V, VIL max 0.8 V at VCC 4.5-5.5 V). |
| 18 | 1Y0 | output | Output of the first buffer; it presents the inverted 1A0 data when 1OE is low and goes high-impedance when 1OE is high, with ±24 mA drive at 5 V. |
| 19 | 2OE | input | Active-low output enable for the second 4-bit buffer; pulling 2OE high places all second-buffer outputs (2Y0-2Y3) in the 3-state mode. |
| 20 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V (4.5 V ≤ VCC ≤ 5.5 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu RUNIC Tech |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | | 5.5 | V | | 8 |
| High-level input voltage | VIH | 2 | | | V | VCC=4.5V to 5.5V | 8 |
| Low-level input voltage | VIL | | | 0.8 | V | VCC=4.5V to 5.5V | 8 |
| Input voltage | VI | 0 | | | V | | 8 |
| Output voltage | VO | 0 | | | V | | 8 |
| High-level output current | IOH | -24 | | | mA | VCC=4.5V to 5.5V | 8 |
| Low-level output current | IOL | | | 24 | mA | VCC=4.5V to 5.5V | 8 |
| Input transition rise or fall rate | Δt/Δv | | | 8 | ns/V | VCC=4.5V to 5.5V | 8 |
| Operating free-air temperature | TA | -40 | | 125 | °C | | 8 |
| Supply voltage range | VCC | -0.5 | | 6.5 | V | | 7 |
| Input voltage range | VI | -0.5 | | 6.5 | V | | 7 |
| Output voltage range | VO | -0.5 | | | V | | 7 |
| Input clamp current | IIK | -50 | | | mA | VI<0 | 7 |
| Output clamp current | IOK | -50 | | | mA | Vo<0 | 7 |
| Continuous output current | IO | -50 | | 50 | mA | | 7 |
| Continuous current through VCC or GND | | -100 | | 100 | mA | | 7 |
| Junction temperature | TJ | -40 | | 150 | °C | | 7 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 7 |
| Package thermal impedance, SOP20 | θJA | | | 40 | °C/W | SOP20 package, calculated per JESD-51 | 7 |
| Output high voltage, 50 µA | VOH | 4.4 | | | V | IOH = -50µA; VCC=4.5V; Full | 8 |
| Output high voltage, 50 µA | VOH | 5.4 | | | V | IOH = -50µA; VCC=5.5V; Full | 8 |
| Output high voltage, 24 mA | VOH | 3.76 | | | V | IOH = -24mA; VCC=4.5V | 8 |
| Output high voltage, 24 mA | VOH | 4.76 | | | V | IOH = -24mA; VCC=5.5V | 8 |
| Output high voltage, 50 mA | VOH | 3.85 | | | V | IOH = -50mA; VCC=5.5V | 8 |
| Output low voltage, 50 µA | VOL | | | 0.1 | V | IOL = 50µA; VCC=4.5V | 8 |
| Output low voltage, 24 mA | VOL | | | 0.73 | V | IOL = 24mA; VCC=4.5V | 8 |
| Output low voltage, 24 mA | VOL | | | 0.69 | V | IOL = 24mA; VCC=5.5V | 8 |
| Output low voltage, 50 mA | VOL | | | 1.65 | V | IOL = 50mA; VCC=5.5V | 8 |
| Input current | II | -1 | | 1 | µA | VI = VCC or GND; VCC 5.5V; +25C | 8 |
| Input current | II | -2 | | 2 | µA | VI = VCC or GND; VCC 5.5V; Full | 8 |
| Power-off leakage current | Ioff | -1 | | 1 | µA | VI or VO= 0 to 5.5V; VCC 0V; +25C | 8 |
| Power-off leakage current | Ioff | -2 | | 2 | µA | VI or VO= 0 to 5.5V; VCC 0V; Full | 8 |
| Off-state (high-impedance) output current | IOZ | -1 | | 1 | µA | VO = VCC or GND, VI = VIH or VIL; VCC 5.5V; +25C | 8 |
| Off-state (high-impedance) output current | IOZ | -2.5 | | 2.5 | µA | VO = VCC or GND, VI = VIH or VIL; VCC 5.5V; Full | 8 |
| Quiescent supply current | ICC | | | 40 | µA | VI = VCC or GND; IO = 0; VCC 5.5V; Full | 8 |
| Additional supply current per input | ΔICC | | | 1.5 | mA | One input at 3.4 V, Other inputs at GND or VCC; VCC 5.5V; Full | 8 |
| Propagation delay tPLH, An to Yn | tPLH | 2.3 | 5 | 8 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Propagation delay tPLH, An to Yn | tPLH | 2.2 | | 9.2 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
| Propagation delay tPHL, An to Yn | tPHL | 2.2 | 4.9 | 7.9 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Propagation delay tPHL, An to Yn | tPHL | 2.1 | | 8.9 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
| Disable time tPHZ, OE to Yn | tPHZ | 1.9 | 4.5 | 7.7 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Disable time tPHZ, OE to Yn | tPHZ | 1.8 | | 8.3 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
| Disable time tPLZ, OE to Yn | tPLZ | 2.4 | 5.3 | 8.3 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Disable time tPLZ, OE to Yn | tPLZ | 2.2 | | 9.8 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
| Enable time tPZH, OE to Yn | tPZH | 2.8 | 6.3 | 11.9 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Enable time tPZH, OE to Yn | tPZH | 1.8 | | 12.9 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
| Enable time tPZL, OE to Yn | tPZL | 1.2 | 3.3 | 5.6 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 9 |
| Enable time tPZL, OE to Yn | tPZL | 0.9 | | 9.4 | ns | VCC = 5 V ± 0.5 V; TA = -40 ~ 125°C | 9 |
## CAD (KiCad official)
- Symbol: `RS240TXS20`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `rs240txs20-etched.step` / `rs240txs20-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rs240txs20.step` / `rs240txs20.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Jiangsu RUNIC Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603367082348060672) (15 pp, sha256 `7ca59235985e3ec5`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rs240txs20-datasheet.pdf)