RS1G74XVS8

{
  "slug": "rs1g74xvs8",
  "version": "0.1.0",
  "type": "component",
  "description": "Jiangsu RUNIC Tech Logic Gates, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "rs1g74xvs8",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "rs1g74xvs8.kicad_sym",
    "rs1g74xvs8.kicad_mod",
    "rs1g74xvs8.glb",
    "rs1g74xvs8.step",
    "rs1g74xvs8.lbr",
    "docs/hero.png",
    "docs/rs1g74xvs8-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "rs1g74xvs8-hero.glb",
    "rs1g74xvs8-hero.overlay.json",
    "rs1g74xvs8-etched.glb"
  ],
  "component": {
    "mpn": "RS1G74XVS8",
    "manufacturer": "Jiangsu RUNIC Tech",
    "package": "VSSOP-8",
    "pin_count": 8,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757137593123115008",
    "parts": {
      "symbol": "rs1g74xvs8.kicad_sym",
      "footprint": "rs1g74xvs8.kicad_mod",
      "model_3d": "rs1g74xvs8-hero.glb",
      "model_3d_plain": "rs1g74xvs8-etched.glb",
      "model_3d_step": "rs1g74xvs8-etched.step",
      "model_3d_step_plain": "rs1g74xvs8.step",
      "lbr": "rs1g74xvs8.lbr"
    },
    "distributor_links": {
      "lcsc": "C7502506"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T18:36:19Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CLK",
        "type": "input",
        "description": "Clock input; the D input is transferred to the outputs on the positive-going edge of this clock when PRE̅ and CLR̅ are inactive (high), and inputs accept up to 5.5 V."
      },
      {
        "number": "2",
        "name": "D",
        "type": "input",
        "description": "Data input that is transferred to Q on the positive clock edge when PRE̅ and CLR̅ are high and setup/hold times are met; inputs accept up to 5.5 V."
      },
      {
        "number": "3",
        "name": "Q̅",
        "type": "output",
        "description": "Inverted output; High-Level Output Current is -24 mA at VCC=3.0 V and Low-Level Output Current is 24 mA at VCC=3.0 V, with ±50 mA maximum continuous output current."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "5",
        "name": "Q",
        "type": "output",
        "description": "Output; High-Level Output Current is -24 mA at VCC=3.0 V and Low-Level Output Current is 24 mA at VCC=3.0 V, with ±50 mA maximum continuous output current."
      },
      {
        "number": "6",
        "name": "CLR̅",
        "type": "input",
        "description": "Active-low clear input; pulling it low sets Q low regardless of the other inputs, and inputs accept up to 5.5 V."
      },
      {
        "number": "7",
        "name": "PRE̅",
        "type": "input",
        "description": "Active-low preset input; pulling it low sets Q high regardless of the other inputs, and inputs accept up to 5.5 V."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; the recommended operating range is 1.65 V to 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The VSSOP8 top-view pin diagram in the extracted text is garbled, so pin numbers were taken from the; Pin 3 (Q̅) and pins 6 and 7 (CLR̅, PRE̅) have overbars in the source that did not extract cleanly; n; The datasheet does not state a per-pin voltage limit for pins 3, 4, 5 and 8 beyond the absolute-maxi"
        ],
        "pages_sent": 19,
        "cost_usd": 0.06,
        "at": "2026-10-17T18:34:26"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757137593123115008",
        "pages": 19,
        "sha256": "788e156472fe548f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "rs1g74xvs8.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.1,
          2.0,
          0.85
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "rs1g74xvs8-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.1,
          2.0,
          0.85
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5637f76d8ef4e4abed0cfb18572d8150cdb25912d9e8927d74261d02b503bb71",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}