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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs rs1g14xc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 13d ago
README.md rs1g14xc5: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago
rs1g14xc5-etched.fit.json rs1g14xc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
rs1g14xc5-etched.glb rs1g14xc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
rs1g14xc5-etched.step rs1g14xc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
rs1g14xc5.glb Publish 0.1.0 · Ray 1mo ago
rs1g14xc5.kicad_mod Publish 0.1.0 · Ray 1mo ago
rs1g14xc5.kicad_sym Publish 0.1.0 · Ray 1mo ago
rs1g14xc5.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 5 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
rs1g14xc5.step Publish 0.1.0 · Ray 1mo ago

RS1G14XC5

Jiangsu RUNIC Tech · Inverters · SC70-5

RS1G14XC5 from Jiangsu RUNIC Tech, in a SC70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N.C. unconnected Not connected. Leave floating or tie to VCC/GND per board convention.
2 A input Schmitt-trigger logic input. Accepts input voltages up to 5.5V regardless of VCC (5V-tolerant). Positive-going threshold VT+ and negative-going threshold VT- create hysteresis (e.g. ~1.05V at VCC=3V) for clean switching on slow/noisy edges.
3 GND power_in Ground reference (0 V) for the device.
4 Y output Inverted logic output (Y = /A). Push-pull CMOS output capable of ±24 mA drive at VCC = 3.0V. Output voltage range 0 to VCC.
5 VCC power_in Positive supply voltage. Operating range 1.65 V to 5.5 V; absolute maximum 6.5 V. Data-retention minimum 1.5 V. Quiescent supply current ICC ≤ 1 µA (typ 0.1 µA).

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package SC70-5
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • RS1G14XC5
  • RS1G14XC5XF5

CAD (KiCad official)

  • Symbol: RS1G14XC5
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC70-5 (KiCad packages3D, STEP)
  • 3D model files: rs1g14xc5-etched.step / rs1g14xc5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs1g14xc5.step / rs1g14xc5.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
rs1g14xc5.step 87 KB You want the bare part, or you mark your own boards.
rs1g14xc5-etched.step 1.8 MB You want the part with RS1G14XC5 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 443 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (11 pp, sha256 45f33b07ea57b9cd, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF