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RS1472XTQC16

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Jiangsu RUNIC Tech Analog To Digital Converters (ADCs), QFN-16L(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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RS1472XTQC16

Jiangsu RUNIC Tech · Analog To Digital Converters (ADCs) · QFN-16L(3x3)

RS1472XTQC16 from Jiangsu RUNIC Tech, in a QFN-16L(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power supply ground.
2 AVDD power_in ADC power supply, recommended range 2.7 V to 5.25 V.
3 REF input ADC positive reference input, decouple this pin with REFGND.
4 REFGND passive Reference return; short to analog ground plane.
5 AIN0P input Positive analog input, channel 0.
6 AIN0N input Negative analog input, channel 0.
7 AIN1N input Negative analog input, channel 1.
8 AIN1P input Positive analog input, channel 1.
9 NC unconnected Not connected internally, recommended to short this pin to GND.
10 NC unconnected Not connected internally, recommended to short this pin to GND.
11 CH_SEL input Selects the analog input channel (Low = Channel 0, High = Channel 1); change within one clock window starting half a clock after the CS falling edge.
12 PDEN input Enables a power down feature if it is high at the CS rising edge.
13 CS input Chip select signal, active low.
14 SCLK input Serial SPI clock.
15 SDO output Serial data out.
16 DVDD power_in Digital I/O supply, 1.65 V to AVDD.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package QFN-16L(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage AVDD, DVDD to GND -0.3 6 V AVDD to GND, DVDD to GND 6
Digital input voltage to GND -0.3 V upper limit printed as DVDD+0.3 6
Digital output pin voltage (CS, SCLK, SDO) -0.3 V upper limit printed as DVDD+0.3 6
Signal input pin current -10 10 mA 6
Package thermal impedance θJA 70 °C/W QFN3×3-16 6
Operating temperature range TA -40 125 °C 6
Junction temperature TJ -40 150 °C 6
Storage temperature Tstg -65 150 °C 6
ESD HBM V(ESD) -2000 2000 V Human-body model, ANSI/ESDA/JEDEC JS-001 6
ESD CDM V(ESD) -500 500 V Charged-device model, ANSI/ESDA/JEDEC JS-002 6
ESD MM V(ESD) -200 200 V Machine model 6
Analog supply voltage AVDD 2.7 3.3 5.25 V AVDD to GND 6
Digital supply voltage DVDD 1.65 3.3 V DVDD to GND; max printed as AVDD 6
Operating ambient temperature TA -40 125 °C 6
Absolute input range AIN0P, AIN1P -0.2 V max printed as AVDD + 0.2 7
Absolute input range AIN0N, AIN1N -0.2 V max printed as AVDD + 0.2 7
Input capacitance 36 pF 7
Input leakage current 1 uA At +125°C 7
Resolution 14 Bits 7
No missing codes 14 Bits 7
Integral nonlinearity INL -2.5 0.8 2.5 LSB typ printed as ±0.8 7
Differential linearity DNL -1 0.6 1.5 LSB typ printed as ±0.6 7
Offset error -4 1.5 4 LSB typ printed as ±1.5 7
Gain error -4 2 4 LSB typ printed as ±2 7
Transition noise 60 μVRMS 7
Power-supply rejection 60 dB With 500 Hz sine wave on AVDD 7
Total harmonic distortion THD -92 dB 20kHz, VREF = 4.096V 7
Signal to noise ratio SNR 82 84 dB 20kHz, VREF = 4.096V 7
Signal to noise ratio SNR 83 dB 100k Hz, VREF = 4.096V 7
Signal to noise and distortion ratio SINAD 84 dB 20kHz, VREF = 4.096V 7
Spurious-free range SFDR 94 dB 20kHz, VREF = 4.096V 7
Full power bandwidth 20 MHz At -1dB 7
Maximum sample rate (throughput rate) 2 MSPS 40 MHz SCLK with a 16-clock frame 7
Aperture delay 10 ns 7
Input leakage current (digital) ILEAK -1 1 μA 0 < VIN < DVDD 8
External reference 2.5 V max printed as AVDD 8
Analog Supply Voltage AVDD 2.7 3.3 5.25 V 8
Digital Supply Voltage DVDD 1.65 3.3 V max printed as AVDD 8
Analog supply current IAVDD 3.6 4.2 mA AVDD = 3.3V, fSAMPLE = 2MSPS 8
Analog supply current IAVDD 4.5 5.5 mA AVDD = 5V, fSAMPLE = 2MSPS 8
Analog supply current IAVDD 3 3.5 mA AVDD = 5V, SCLK off 8
Power down state AVDD supply current IPD 500 μA SCLK = 40 MHz 8
Power down state AVDD supply current IPD 2.5 μA SCLK off 8
Power up time PST 0.3 1 μs From power down state using PDEN pin 8
Specified performance temperature TA -40 125 °C 8
Pulse width CS high tW1 25 ns 9
Setup time, CS low to first rising edge of SCLK tSU1 3.5 ns DVDD = 1.8V, 3V, 5V 9
Pulse duration, SCLK high tWH 8 ns 9
Pulse duration, SCLK low tWL 8 ns 9
SCLK frequency 40 MHz 9
Setup time, PDEN high to CS rising edge tPDSU 2 ns 9
Hold time, CS rising edge to PDEN falling edge tPDH 20 ns 9

CAD (KiCad official)

  • Symbol: RS1472XTQC16
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: QFN-16L(3x3) (KiCad packages3D, STEP)
  • 3D model files: rs1472xtqc16-etched.step / rs1472xtqc16-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs1472xtqc16.step / rs1472xtqc16.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (28 pp, sha256 9b2a598585e967bc, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF