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RS1461XH

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Jiangsu RUNIC Tech Analog To Digital Converters (ADC), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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RS1461XH

Jiangsu RUNIC Tech · Analog To Digital Converters (ADC) · SOT-23-6

RS1461XH from Jiangsu RUNIC Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply pin, specified for a quiet 2.7 V to 5.25 V source, bypassed to GND with 0.1 µF and 1 µF monolithic capacitors placed within 1 cm of the pin; it also serves as the ADC reference, so it must be thoroughly bypassed.
2 GND power_in Ground return for the supply.
3 VIN power_in Analog input whose signal can range from 0 V to VDD.
4 SCLK input Digital clock input with a frequency range of 10 kHz to 20 MHz (performance ensured at 20 MHz), which directly controls the conversion and readout processes.
5 SDATA output Digital data output; output words are clocked out of this pin by SCLK, and the pin goes to TRI-STATE when not transferring data.
6 CS input Chip select (active low, shown as CS̅ on the datasheet); a conversion begins on the falling edge of CS̅ and it frames the serial data transfer.

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package SOT-23-6
Category Data Acquisition
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VDD VDD -0.3 6.5 V 6
Voltage on any analog pin to GND -0.3 V 6
Voltage on any digital pin to GND -0.3 6.5 V 6
Input current at any pin (except power supply pins) -10 10 mA 6
Package thermal impedance, SOT-23-6 θJA 230 °C/W 6
Soldering temperature, infrared (10 sec) 215 °C 6
Operating temperature TA 150 °C 6
Storage temperature Tstg -65 150 °C 6
Supply voltage VDD 2.7 5.25 V 6
Digital input pins voltage (independent of supply voltage) 2.7 5.25 V 6
Operating temperature TA -40 125 °C 6
Integral non-linearity INL -1 0.6 1 LSB -40°C ≤TA ≤ 125°C 7
Differential non-linearity DNL -0.8 1 LSB -40°C ≤TA ≤ 125°C 7
Offset error VOFF -2 1.2 2 LSB -40°C ≤TA ≤ 125°C 7
Gain error GE -1.2 0.6 1.2 LSB -40°C ≤TA ≤ 125°C 7
Total Unadjusted Error TUE -1.2 1.2 LSB -40°C ≤TA ≤ 125°C 7
Signal-to-noise plus distortion ratio SINAD 70 71.5 dB fIN=100kHz, -40°C ≤TA ≤ 125°C 7
Signal-to-noise ratio SNR 70.5 72 dB fIN=100kHz, -40°C ≤TA ≤ 125°C 7
Normal mode (static) supply current IDD 1 mA VDD = 4.75V to 5.25V, SCLK On or Off 7
Normal mode (static) supply current IDD 0.9 mA VDD = 2.7V to 3.6V, SCLK On or Off 7
Normal mode (operational) supply current IDD 2.2 3 mA VDD = 4.75V to 5.25V, fSAMPLE = 1MSPS, -40°C ≤TA ≤ 125°C 7
Normal mode (operational) supply current IDD 1.5 2 mA VDD = 2.7V to 3.6V, fSAMPLE = 1MSPS, -40°C ≤TA ≤ 125°C 7
Shutdown mode supply current IDD 1 µA VDD = 5V, SCLK Off 7
Shutdown mode supply current IDD 50 µA VDD = 5V, SCLK On 7
Power consumption, normal mode (operational) PD 11 15 mW VDD = 5V, fSAMPLE = 1MSPS, -40°C ≤TA ≤ 125°C 7
Power consumption, normal mode (operational) PD 4.5 6 mW VDD = 3V, fSAMPLE = 1MSPS, -40°C ≤TA ≤ 125°C 7
Power consumption, shutdown mode PD 5 µW VDD = 5V, SCLK Off 7
Power consumption, shutdown mode PD 3 µW VDD = 3V, SCLK Off 7
Input range VIN 0 V 7
DC leakage current IDCL -1 1 µA 7
Input high voltage VIH 2.4 V -40°C ≤ TA≤ 125°C 7
Input low voltage VIL 0.8 V VDD = 5V, -40°C ≤TA ≤ 125°C 7
Input low voltage VIL 0.4 V VDD = 3V, -40°C ≤TA ≤ 125°C 7
Input current IIN -100 100 nA VIN = 0V or VDD 8
Output low voltage VOL 0.4 V ISINK = 200µA, -40°C ≤TA ≤ 125°C 8
TRI-STATE leakage current IOL -10 10 µA -40°C ≤TA ≤ 125°C 8
Clock frequency fSCLK 20 MHz -40°C ≤TA ≤ 125°C 8
DC SCLK duty cycle DC 40 60 % -40°C ≤TA ≤ 85°C 8
Quiet time tQUIET 50 ns 8
Minimum CS pulse width t1 10 ns 8
CS to SCLK setup time t2 10 ns 8
Delay from CS until SDATA TRI-STATE disabled t3 20 ns Measured with 25pF load 8
Data access time after SCLK falling edge t4 40 ns VDD = 2.7V to 3.6V; measured with 25pF load 8
Data access time after SCLK falling edge t4 20 ns VDD = 4.75V to 5.25V; measured with 25pF load 8
SCLK to data valid hold time t7 7 ns VDD = 2.7V to 3.6V 8
SCLK to data valid hold time t7 5 ns VDD = 4.75V to 5.25V 8
SCLK falling edge to SDATA high impedance t8 6 25 ns VDD = 2.7V to 3.6V 8
SCLK falling edge to SDATA high impedance t8 5 25 ns VDD = 4.75V to 5.25V 8

CAD (KiCad official)

  • Symbol: RS1461XH
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: rs1461xh-etched.step / rs1461xh-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs1461xh.step / rs1461xh.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (21 pp, sha256 8a9c9ac1ba5e3ef7, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF