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RP2350A

Public Made by Adom

by adom

Raspberry Pi Microcontrollers, QFN-60-EP(7x7). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.

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RP2350A

Raspberry Pi · Microcontrollers · QFN-60-EP(7x7)

RP2350A from Raspberry Pi, in a QFN-60-EP(7x7). Symbol, footprint and 3D model are the ones used on Adom board designs (3D model: KiCad library 3D model QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm (built with the KiCad generator) (CC-BY-SA 4.0 with the KiCad library exception)). Pin functions are extracted from the manufacturer datasheet with page references.

Pinout

Pin Name Type Function
1 IOVDD power_in Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1330]
2 GPIO0 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Default drive 4 mA; programmable pull-up/pull-down, slew rate, Schmitt trigger. Reset state: pull-down. Muxable to SPI0_RX / UART0_TX / I2C0_SDA / PWM0_A / SIO / PIO0..2 / QMI_CS1n / USB OVCUR DET. [datasheet p.1332]
3 GPIO1 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_CSn / UART0_RX / I2C0_SCL / PWM0_B / SIO / PIO0..2 / TRACECLK / USB VBUS DET. [datasheet p.1332]
4 GPIO2 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_SCK / UART0_CTS / I2C1_SDA / PWM1_A / SIO / PIO0..2 / TRACEDATA0 / USB VBUS EN / UART0_TX. [datasheet p.1332]
5 GPIO3 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_TX / UART0_RTS / I2C1_SCL / PWM1_B / SIO / PIO0..2 / TRACEDATA1 / USB OVCUR DET / UART0_RX. [datasheet p.1332]
6 DVDD power_in Digital core supply, nominal 1.1 V. Must be driven externally — either from the on-chip VREG output (VREG_LX filtered to DVDD) or from an off-chip 1.1 V rail. One of three DVDD pins (6, 23, 39). [datasheet p.1334]
7 GPIO4 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_RX / UART1_TX / I2C0_SDA / PWM2_A / SIO / PIO0..2 / TRACEDATA2 / USB VBUS DET. [datasheet p.1332]
8 GPIO5 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_CSn / UART1_RX / I2C0_SCL / PWM2_B / SIO / PIO0..2 / TRACEDATA3 / USB VBUS EN. [datasheet p.1332]
9 GPIO6 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_SCK / UART1_CTS / I2C1_SDA / PWM3_A / SIO / PIO0..2 / USB OVCUR DET / UART1_TX. [datasheet p.1332]
10 GPIO7 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_TX / UART1_RTS / I2C1_SCL / PWM3_B / SIO / PIO0..2 / USB VBUS DET / UART1_RX. [datasheet p.1332]
11 IOVDD power_in Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1334]
12 GPIO8 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_RX / UART1_TX / I2C0_SDA / PWM4_A / SIO / PIO0..2 / QMI_CS1n / USB VBUS EN. [datasheet p.1332]
13 GPIO9 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_CSn / UART1_RX / I2C0_SCL / PWM4_B / SIO / PIO0..2 / USB OVCUR DET. [datasheet p.1332]
14 GPIO10 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_SCK / UART1_CTS / I2C1_SDA / PWM5_A / SIO / PIO0..2 / USB VBUS DET / UART1_TX. [datasheet p.1332]
15 GPIO11 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_TX / UART1_RTS / I2C1_SCL / PWM5_B / SIO / PIO0..2 / USB VBUS EN / UART1_RX. [datasheet p.1332]
16 GPIO12 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_RX / UART0_TX / I2C0_SDA / PWM6_A / SIO / PIO0..2 / CLOCK GPIN0 / USB OVCUR DET. [datasheet p.1332]
17 GPIO13 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_CSn / UART0_RX / I2C0_SCL / PWM6_B / SIO / PIO0..2 / CLOCK GPOUT0 / USB VBUS DET. [datasheet p.1332]
18 GPIO14 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_SCK / UART0_CTS / I2C1_SDA / PWM7_A / SIO / PIO0..2 / CLOCK GPIN1 / USB VBUS EN / UART0_TX. [datasheet p.1332]
19 GPIO15 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_TX / UART0_RTS / I2C1_SCL / PWM7_B / SIO / PIO0..2 / CLOCK GPOUT1 / USB OVCUR DET / UART0_RX. [datasheet p.1332]
20 IOVDD power_in Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1334]
21 XIN input Crystal oscillator input. Attach a crystal (typically 12 MHz for the stock USB bootloader) between XIN and XOUT with the recommended load capacitors; or drive XIN with a square-wave CMOS clock (0.65*IOVDD to IOVDD+0.3 V high) with XOUT left floating. XOSC input range 1-50 MHz. [datasheet p.1334]
22 XOUT passive Crystal oscillator output. Connect to the far side of the crystal with load capacitor to ground. Leave floating when XIN is driven by an external clock. [datasheet p.1334]
23 DVDD power_in Digital core supply, nominal 1.1 V. Must be driven externally — either from the on-chip VREG output (VREG_LX filtered to DVDD) or from an off-chip 1.1 V rail. One of three DVDD pins (6, 23, 39). [datasheet p.1334]
24 SWCLK input Serial Wire Debug clock input (Fault-Tolerant). Pull-up at reset. SWD operates reliably up to 50 MHz on-chip (external signal integrity may limit practical rate). [datasheet p.1334]
25 SWDIO bidirectional Serial Wire Debug data input/output (Fault-Tolerant). Pull-up at reset. Pairs with SWCLK for the SWD debug port; connect to the debug probe's SWDIO. [datasheet p.1334]
26 RUN input Global asynchronous active-low reset input (Fault-Tolerant). Drive low to hold chip in reset; release high to run. Pull-up at reset. If no external reset is needed, tie directly to IOVDD. [datasheet p.1334]
27 GPIO16 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_RX / UART0_TX / I2C0_SDA / PWM0_A / SIO / PIO0..2 / USB VBUS DET. [datasheet p.1332]
28 GPIO17 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_CSn / UART0_RX / I2C0_SCL / PWM0_B / SIO / PIO0..2 / USB VBUS EN. [datasheet p.1332]
29 GPIO18 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_SCK / UART0_CTS / I2C1_SDA / PWM1_A / SIO / PIO0..2 / USB OVCUR DET / UART0_TX. [datasheet p.1332]
30 IOVDD power_in Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1334]
31 GPIO19 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_TX / UART0_RTS / I2C1_SCL / PWM1_B / SIO / PIO0..2 / QMI_CS1n / USB VBUS DET / UART0_RX. [datasheet p.1332]
32 GPIO20 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_RX / UART1_TX / I2C0_SDA / PWM2_A / SIO / PIO0..2 / CLOCK GPIN0 / USB VBUS EN. [datasheet p.1332]
33 GPIO21 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_CSn / UART1_RX / I2C0_SCL / PWM2_B / SIO / PIO0..2 / CLOCK GPOUT0 / USB OVCUR DET. [datasheet p.1332]
34 GPIO22 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_SCK / UART1_CTS / I2C1_SDA / PWM3_A / SIO / PIO0..2 / CLOCK GPIN1 / USB VBUS DET / UART1_TX. [datasheet p.1332]
35 GPIO23 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_TX / UART1_RTS / I2C1_SCL / PWM3_B / SIO / PIO0..2 / CLOCK GPOUT1 / USB VBUS EN / UART1_RX. [datasheet p.1332]
36 GPIO24 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_RX / UART1_TX / I2C0_SDA / PWM4_A / SIO / PIO0..2 / CLOCK GPOUT2 / USB OVCUR DET. [datasheet p.1332]
37 GPIO25 bidirectional General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_CSn / UART1_RX / I2C0_SCL / PWM4_B / SIO / PIO0..2 / CLOCK GPOUT3 / USB VBUS DET. [datasheet p.1332]
38 IOVDD power_in Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1334]
39 DVDD power_in Digital core supply, nominal 1.1 V. Must be driven externally — either from the on-chip VREG output (VREG_LX filtered to DVDD) or from an off-chip 1.1 V rail. One of three DVDD pins (6, 23, 39). [datasheet p.1334]
40 GPIO26_ADC0 bidirectional GPIO26 or ADC channel 0 input. Digital IO + Analogue input domain (IOVDD / ADC_AVDD). Full ADC range 0 V to ADC_AVDD (nominal 3.3 V). 12-bit SAR ADC, 100 kΩ input impedance; keep input ≤ IOVDD to avoid ESD-diode leakage. [datasheet p.1332]
41 GPIO27_ADC1 bidirectional GPIO27 or ADC channel 1 input. Digital IO + Analogue input. Same characteristics as ADC0: 12-bit, 0 V to ADC_AVDD. [datasheet p.1332]
42 GPIO28_ADC2 bidirectional GPIO28 or ADC channel 2 input. Digital IO + Analogue input. 12-bit SAR, 0 V to ADC_AVDD. [datasheet p.1332]
43 GPIO29_ADC3 bidirectional GPIO29 or ADC channel 3 input. Digital IO + Analogue input. 12-bit SAR, 0 V to ADC_AVDD. [datasheet p.1333]
44 ADC_AVDD power_in Analogue supply for the ADC and reference. Nominal 3.3 V. Must be powered whenever any ADC input is used. Low-noise bulk/decoupling recommended; can share source with VREG_AVDD/IOVDD at 3.3 V with filtering. [datasheet p.1334]
45 IOVDD power_in Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1334]
46 VREG_AVDD power_in Analogue supply for the on-chip core voltage regulator and power-on-reset / brownout detection. Nominal 3.3 V. Must be powered even when the regulator is disabled. Can share source with VREG_VIN or IOVDD at 3.3 V, with careful decoupling. [datasheet p.1334]
47 VREG_PGND power_in Power ground return for the internal switched-mode core voltage regulator. Tie externally to the main GND plane (dedicated short/low-impedance path recommended because switcher currents flow here). [datasheet p.1334]
48 VREG_LX power_out Switching-node output of the on-chip buck regulator. Connect to the external inductor of the buck filter network (inductor + output capacitor to GND, feedback to VREG_FB). Nominal 1.1 V after LC filtering; max 200 mA. [datasheet p.1334]
49 VREG_VIN power_in Input supply for the internal core voltage regulator (both buck and low-quiescent LDO modes). Range 2.7 V to 5.5 V. Bulk + ceramic decoupling at the pin. [datasheet p.1334]
50 VREG_FB input Feedback input for the on-chip core voltage regulator. Connect to the filtered regulator output (typically DVDD) so the regulator senses the actual core voltage after the inductor and output cap. [datasheet p.1335]
51 USB_DM bidirectional USB 1.1 Full/Low Speed D- signal. External 27 Ω series termination required for USB operation. Internal pull-ups/pull-downs are provided per the USB spec. May be reused as a software-controlled GPIO when USB is not used. [datasheet p.1334]
52 USB_DP bidirectional USB 1.1 Full/Low Speed D+ signal. External 27 Ω series termination required for USB operation. Powered by USB_OTP_VDD. [datasheet p.1334]
53 USB_OTP_VDD power_in Supply rail for the on-chip USB Full-Speed PHY and OTP storage. Nominal 3.3 V. Decouple close to the pin; USB_DP/USB_DM referenced to this rail. [datasheet p.1334]
54 QSPI_IOVDD power_in Supply for the dedicated QSPI IO pads (QSPI_SS, QSPI_SCLK, QSPI_SD0..3). Nominal 1.8 V to 3.3 V (2.7-3.6 V when driving an internal flash die in RP2354A). Must match the external flash/PSRAM Vcc. [datasheet p.1334]
55 QSPI_SD3 bidirectional QSPI data line 3 (dedicated XIP interface). Pull-up at reset. In single-SPI mode this doubles as /HOLD or /RESET on standard NOR flash. May be used as a software-controlled GPIO if the QSPI bus is not used. [datasheet p.1333]
56 QSPI_SCLK output QSPI clock output to external flash/PSRAM (and internal flash die in RP2354A). Pull-down at reset. Max 133 MHz when paired with W25Q16JV. [datasheet p.1333]
57 QSPI_SD0 bidirectional QSPI data line 0 (MOSI in single-SPI mode). Pull-down at reset. [datasheet p.1333]
58 QSPI_SD2 bidirectional QSPI data line 2. In single-SPI mode doubles as /WP on standard NOR flash. Pull-up at reset. [datasheet p.1333]
59 QSPI_SD1 bidirectional QSPI data line 1 (MISO in single-SPI mode). Pull-down at reset. If held high while QSPI_SS is low on power-up, selects UART-boot BOOTSEL mode (UART TX on SD2, RX on SD3). [datasheet p.1333]
60 QSPI_SS bidirectional QSPI chip-select (active low). Pull-up at reset. If held low during reset the chip enters BOOTSEL mode (USB mass-storage/UART boot). Supports an external second QSPI device via a secondary CSn from Bank 0. [datasheet p.1333]
61 GND power_in Central exposed pad — single external ground connection, bonded to all internal ground pads. Must be soldered to the PCB ground plane for proper electrical operation and thermal conduction (θJB ≈ 12.6 °C/W). [datasheet p.1335]

Key specifications

Parameter Value
Manufacturer Raspberry Pi
Package QFN-60-EP(7x7)
Category Embedded Processors & Controllers
Pins 61
LCSC C42411118
Ordering code SC1509-A4 (7" reel of 500), SC1509(13)-A4 (13" reel of 3400)
DigiKey 2648-SC1509-A4TR-ND (7" reel), 2648-SC1509(13)TR-ND (13" reel)
Mouser 358-SC1509 (7" reel), 358-SC150913 (13" reel)

CAD

  • Symbol: rp2350a (source library MCU_RaspberryPi_RP2350:RP2350_60QFN)
  • Footprint: RPi_CDT:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm_RP2350a
  • 3D model path in footprint: ${KIPRJMOD}/rp2350a.step
  • 3D files: rp2350a-etched.step / rp2350a-etched.glb carry the MPN etch as a separate Adom.LaserEtch part; rp2350a.step / rp2350a.glb are the bare model.
  • EAGLE/Fusion library: rp2350a.lbr (adom-lbr)

Provenance

  • Datasheet: Raspberry Pi RP2350 datasheet (build-date 2026-10-01, sha256 a638d6780da91916, retrieved 2026-10-27, tier: mfr)
  • CAD: Footprint and symbol as used on Adom board designs; 3D model: KiCad library 3D model QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm (built with the KiCad generator) (CC-BY-SA 4.0 with the KiCad library exception).
  • Pins: KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7).

Datasheet PDF