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RP170N501D-TR-FE
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Nisshinbo Micro Devices Inc Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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RP170N501D-TR-FE
Nisshinbo Micro Devices Inc · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
RP170N501D-TR-FE from Nisshinbo Micro Devices Inc, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Input pin supplying the LDO; the datasheet specifies an input voltage range of 2.6 V to 10.0 V, with an absolute maximum of 12 V. |
| 2 | GND | power_in | Ground pin for the regulator. |
| 3 | CE | input | Chip enable pin, active high: VCEH is 1.7 V minimum and VCEL is 0.8 V maximum, and the absolute maximum CE input voltage is 12 V. |
| 4 | NC | unconnected | No connection; this pin is not connected internally. |
| 5 | VOUT | power_out | Regulated output pin, rated for an output current of up to 300 mA, with a 330 mA absolute maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nisshinbo Micro Devices Inc |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage (Ta=25°C) | VOUT | 4.95 | 5 | 5.05 | V | Ta=25°C, VIN=Set VOUT+1V, IOUT=1mA; product table for 5.0V (RP170x50xx) | 7 |
| Output Voltage (Ta=-40 to 85°C) | VOUT | 4.87 | 5 | 5.115 | V | -40°C ≤ Ta ≤ 85°C, VIN=Set VOUT+1V, IOUT=1mA; product table for 5.0V (RP170x50xx) | 7 |
| Output Voltage accuracy (Ta=25°C) | VOUT | 0.99 | 1.01 | ×set VOUT | Ta=25°C, VOUT > 1.5V (printed as ×0.99 / ×1.01) | 5 | |
| Output Voltage accuracy (-40 to 85°C) | VOUT | 0.974 | 1.023 | ×set VOUT | -40°C ≤ Ta ≤ 85°C, VOUT > 1.5V (printed as ×0.974 / ×1.023) | 5 | |
| Load Regulation | ΔVOUT/ΔIOUT | 10 | 70 | mV | 0.1mA ≤ IOUT ≤ 300mA | 5 | |
| Dropout Voltage | VDIF | 0.5 | 0.75 | V | IOUT=300mA, 4.0V ≤ VOUT ≤ 6.5V | 5 | |
| Supply Current | ISS | 23 | 40 | µA | IOUT=0mA | 5 | |
| Standby Current | Istandby | 0.1 | 1 | µA | VIN=10.0V, VCE=GND | 5 | |
| Line Regulation | ΔVOUT/ΔVIN | 0.02 | 0.2 | %/V | Set VOUT+0.5V ≤ VIN ≤ 10.0V | 5 | |
| Ripple Rejection | RR | 70 | dB | f=1kHz, Ripple 0.2Vp-p, IOUT=30mA | 5 | ||
| Short Current Limit | ISC | 40 | mA | VOUT=0V | 5 | ||
| Output Current | IOUT | 300 | mA | 5 | |||
| CE Pull-down Current | IPD | 0.3 | µA | 5 | |||
| CE Input Voltage "H" | VCEH | 1.7 | V | 5 | |||
| CE Input Voltage "L" | VCEL | 0.8 | V | 5 | |||
| Thermal Shutdown Temperature | TTSD | 165 | °C | Junction temperature | 5 | ||
| Thermal Shutdown Released Temperature | TTSR | 110 | °C | Junction temperature | 5 | ||
| Output Noise | en | 100 | µVrms | BW=10Hz to 100kHz | 5 | ||
| Low Output Nch Transistor ON Resistance (D version) | RLOW | 250 | Ω | VIN=7.0V, VCE=0V | 5 | ||
| Temperature-Drift Coefficient of Output Voltage | -80 | 80 | 80 | ppm/°C | Printed as Typ. ±80ppm/°C in features; temperature range not stated | 1 | |
| Input Voltage (absolute maximum) | VIN | 12 | V | 4 | |||
| CE Pin Input Voltage (absolute maximum) | VCE | 12 | V | 4 | |||
| Output Voltage (absolute maximum) | VOUT | -0.3 | V | Upper limit printed as VIN+0.3 V | 4 | ||
| Output Current (absolute maximum) | IOUT | 330 | mA | 4 | |||
| Power Dissipation (SOT-23-5) | PD | 660 | mW | SOT-23-5, JEDEC STD. 51-7 | 4 | ||
| Junction Temperature Range | Tj | -40 | 125 | °C | 4 | ||
| Storage Temperature Range | Tstg | -55 | 125 | °C | 4 | ||
| Input Voltage (recommended operating) | VIN | 2.6 | 10 | V | 4 | ||
| Operating Temperature Range | Ta | -40 | 85 | °C | 4 | ||
| Input Capacitor C1 (recommended) | C1 | 1 | µF | Ceramic, between VDD and GND, as close as possible to pins | 8 | ||
| Output Capacitor C2 (recommended) | C2 | 1 | µF | Ceramic, good ESR, as close as possible to VOUT pin | 8 | ||
| Thermal Resistance Junction-to-Ambient (SOT-23-5) | θja | 150 | °C/W | SOT-23-5, JEDEC STD. 51-7 four-layer board, Ta=25°C, Tjmax=125°C | 27 | ||
| Thermal Characterization Parameter Junction-to-Top (SOT-23-5) | ψjt | 51 | °C/W | SOT-23-5, JEDEC STD. 51-7 four-layer board, Ta=25°C, Tjmax=125°C | 27 |
CAD (KiCad official)
- Symbol:
RP170N501D-TR-FE - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
rp170n501d-tr-fe-etched.step/rp170n501d-tr-fe-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rp170n501d-tr-fe.step/rp170n501d-tr-fe.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nisshinbo Micro Devices Inc datasheet (31 pp, sha256
a89b10720f1eba33, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).