component
RL1812A680K
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RUILON Shenzhen Ruilongyuan Elec Varistors, 1812. Unpolarised two-terminal part: the datasheet prints no pin numbers, so pins 1 and 2 follow the library convention, KiCad symbol/footprint/3D.
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RL1812A680K
RUILON Shenzhen Ruilongyuan Elec · Varistors · 1812
RL1812A680K from RUILON Shenzhen Ruilongyuan Elec, in a 1812. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | Terminal 1 of an unpolarised resistor; either orientation. |
| 2 | 2 | passive | Terminal 2 of an unpolarised resistor; either orientation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RUILON Shenzhen Ruilongyuan Elec |
| Package | 1812 |
| Category | Circuit Protection |
| Pins | 2 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Varistor voltage (min) | V1mA | 67.2 | 84 | V | 2 | ||
| Standard tolerance (K suffix) | -10 | 10 | % | K: ±10% | 1 | ||
| Max. allowable voltage (AC) | VAC | 40 | V | 2 | |||
| Max. allowable voltage (DC) | VDC | 56 | V | 2 | |||
| Max. energy | 1.5 | J | 10/1000μs | 2 | |||
| Max. clamping voltage | VC | 184 | V | 8/20μs, IP(A) = 10 | 2 | ||
| Withstanding surge current | I(A) | 800 | A | 8/20μs | 2 | ||
| Varistor voltage change, bias humidity | VV/VV | -10 | 10 | % | 90%RH, 40ºC, working voltage, 1000 hrs | 2 | |
| Varistor voltage change, thermal shock | VV/VV | -10 | 10 | % | -40ºC to 85ºC, 30 min cycle, 5 cycles | 2 | |
| Varistor voltage change, full load | VV/VV | -10 | 10 | % | Working voltage, 85ºC, 1000 hrs | 2 | |
| Operating temperature | -40 | 85 | ºC | 2 | |||
| Storage temperature | -40 | 125 | ºC | Storage | 2 | ||
| Response time | 1 | ns | Printed as <1ns | 2 |
CAD (KiCad official)
- Symbol:
RL1812A680K - Footprint:
Resistor_SMD:R_1812_4532Metric - 3D model: 1812 (KiCad packages3D, STEP)
- 3D model files:
rl1812a680k-etched.step/rl1812a680k-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rl1812a680k.step/rl1812a680k.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RUILON Shenzhen Ruilongyuan Elec datasheet (4 pp, sha256
d2c5ae74098e0d19, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins, primarytwo-terminal convention(convention), consensusoff(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RL1812A680K
**RUILON Shenzhen Ruilongyuan Elec** · Varistors · 1812
RL1812A680K from RUILON Shenzhen Ruilongyuan Elec, in a 1812. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | Terminal 1 of an unpolarised resistor; either orientation. |
| 2 | 2 | passive | Terminal 2 of an unpolarised resistor; either orientation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RUILON Shenzhen Ruilongyuan Elec |
| Package | 1812 |
| Category | Circuit Protection |
| Pins | 2 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Varistor voltage (min) | V1mA | 67.2 | | 84 | V | | 2 |
| Standard tolerance (K suffix) | | -10 | | 10 | % | K: ±10% | 1 |
| Max. allowable voltage (AC) | VAC | | | 40 | V | | 2 |
| Max. allowable voltage (DC) | VDC | | | 56 | V | | 2 |
| Max. energy | | | | 1.5 | J | 10/1000μs | 2 |
| Max. clamping voltage | VC | | | 184 | V | 8/20μs, IP(A) = 10 | 2 |
| Withstanding surge current | I(A) | | | 800 | A | 8/20μs | 2 |
| Varistor voltage change, bias humidity | VV/VV | -10 | | 10 | % | 90%RH, 40ºC, working voltage, 1000 hrs | 2 |
| Varistor voltage change, thermal shock | VV/VV | -10 | | 10 | % | -40ºC to 85ºC, 30 min cycle, 5 cycles | 2 |
| Varistor voltage change, full load | VV/VV | -10 | | 10 | % | Working voltage, 85ºC, 1000 hrs | 2 |
| Operating temperature | | -40 | | 85 | ºC | | 2 |
| Storage temperature | | -40 | | 125 | ºC | Storage | 2 |
| Response time | | | | 1 | ns | Printed as <1ns | 2 |
## CAD (KiCad official)
- Symbol: `RL1812A680K`
- Footprint: `Resistor_SMD:R_1812_4532Metric`
- 3D model: 1812 (KiCad packages3D, STEP)
- 3D model files: `rl1812a680k-etched.step` / `rl1812a680k-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rl1812a680k.step` / `rl1812a680k.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [RUILON Shenzhen Ruilongyuan Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590227039116046336) (4 pp, sha256 `d2c5ae74098e0d19`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `two-terminal convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rl1812a680k-datasheet.pdf)