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docs ref102au: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers ref102au: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json ref102au: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md ref102au: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago
ref102au-etched.fit.json ref102au: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ref102au-etched.glb ref102au: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ref102au-etched.step ref102au: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ref102au.glb Publish 0.1.0 · Ray 1mo ago
ref102au.kicad_mod Publish 0.1.0 · Ray 1mo ago
ref102au.kicad_sym Publish 0.1.0 · Ray 1mo ago
ref102au.lbr Publish 0.1.0 · Ray 1mo ago
ref102au.step Publish 0.1.0 · Ray 1mo ago

REF102AU

Texas Instruments TI · Voltage References · SOIC-8

REF102AU from Texas Instruments TI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection. Leave floating or tie to a copper pad for mechanical support.
2 V+ power_in Positive supply input. Operating range +11.4VDC to +36VDC; absolute maximum input voltage +40V. Quiescent current 1.4mA max at IOUT = 0.
3 NC unconnected No internal connection. Leave floating.
4 Com power_in Common (ground) return for the reference. Establishes the 0V node from which the +10V VOUT is referenced.
5 Trim input Optional user trim input tapping the internal R5 (~50kOhm) divider. Allows small external adjustment of the output voltage with minimal effect on drift and stability; typical trim range approximately +/-3%. Leave floating if unused.
6 VOUT output +10V precision reference output. Initial accuracy +/-10mV (A), +/-5mV (B), +/-2.5mV (C). Sources up to +10mA and sinks up to -5mA; short-circuit protected to Com or V+.
7 NC unconnected No internal connection. Leave floating.
8 NR passive Noise Reduction pin. Ties to the top of the internal ~7kOhm resistor R6 across the zener. Connect an external capacitor from this pin to Com/ground to form a low-pass filter that rolls off high-frequency zener noise. Leave floating for normal (unfiltered) operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments TI
Package SOIC-8
Category Power Management ICs
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • REF102AU
  • REF102BU
  • REF102CU
  • REF102AP
  • REF102BP
  • REF102CP

CAD (KiCad official)

  • Symbol: REF102AU
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ref102au-etched.step / ref102au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ref102au.step / ref102au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments TI datasheet (19 pp, sha256 5860560fea70aa71, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF