# RD3P200SNFRATL

**ROHM Semicon** · MOSFETs · TO-252

RD3P200SNFRATL from ROHM Semicon, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate terminal with ESD protection diode to source; VGSS rating is ±20 V and gate threshold is 1.0 to 2.5 V at VDS = 10 V, ID = 1 mA. |
| 2 | Drain | passive | Drain terminal (also the tab) with VDSS of 100 V and continuous drain current ID of ±20 A (pulsed ±80 A). |
| 3 | Source | passive | Source terminal connected to the body diode anode, with continuous body-diode forward current of 14 A at Ta = 25°C (pulsed 80 A). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | TO-252 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain - Source voltage | VDSS |  |  | 100 | V |  | 1 |
| Continuous drain current | ID | -20 |  | 20 | A | Note *1: limited only by maximum temperature allowed | 1 |
| Pulsed drain current | IDP | -80 |  | 80 | A | Note *2: Pw≦10μs, Duty cycle≦1% | 1 |
| Gate - Source voltage | VGSS | -20 |  | 20 | V |  | 1 |
| Avalanche current, single pulse | IAS |  |  | 10 | A | Note *3: L≒1mH, VDD = 50V, RG = 25Ω, Starting Tj = 25℃ | 1 |
| Avalanche energy, single pulse | EAS |  |  | 72 | mJ | Note *3: L≒1mH, VDD = 50V, RG = 25Ω, Starting Tj = 25℃ | 1 |
| Power dissipation | PD |  |  | 20 | W | Note *4: Tc = 25℃ | 1 |
| Junction temperature | Tj |  |  | 150 | ℃ |  | 1 |
| Operating junction and storage temperature range | Tstg | -55 |  | 150 | ℃ |  | 1 |
| Thermal resistance, junction - case | RthJC |  |  | 6.25 | ℃/W | Note *4: Tc = 25℃ | 2 |
| Drain - Source breakdown voltage | V(BR)DSS | 100 |  |  | V | VGS = 0V, ID = 1mA | 2 |
| Zero gate voltage drain current | IDSS |  |  | 1 | μA | VDS = 100V, VGS = 0V | 2 |
| Gate - Source leakage current | IGSS | -10 |  | 10 | μA | VGS = ±20V, VDS = 0V | 2 |
| Gate threshold voltage | VGS(th) | 1 |  | 2.5 | V | VDS = 10V, ID = 1mA | 2 |
| Static drain - source on - state resistance (VGS = 10V) | RDS(on) |  |  | 46 | mΩ | VGS = 10V, ID = 20A; *5 Pulsed | 2 |
| Static drain - source on - state resistance (VGS = 4.0V) | RDS(on) |  |  | 50 | mΩ | VGS = 4.0V, ID = 20A; *5 Pulsed | 2 |
| Forward transfer admittance | /Yfs/ | 15 |  |  | S | VDS = 10V, ID = 20A; *5 Pulsed | 2 |
| Continuous forward current | IS |  |  | 14 | A | Note *1: Ta = 25℃ | 3 |
| Pulse forward current | ISP |  |  | 80 | A | Note *2: Pw≦10μs, Duty cycle≦1% | 3 |
| Forward voltage | VSD |  |  | 1.5 | V | VGS = 0V, IS = 20A; *5 Pulsed | 3 |

## CAD (KiCad official)

- Symbol: `RD3P200SNFRATL`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files: `rd3p200snfratl-etched.step` / `rd3p200snfratl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rd3p200snfratl.step` / `rd3p200snfratl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ROHM Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912300829261824) (14 pp, sha256 `25b0906061a8f8ee`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rd3p200snfratl-datasheet.pdf)