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RC65D270E

Public Made by Adom

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RealChip(正芯半导体) GaN Transistors(GaN HEMT), TO-252. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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RC65D270E

RealChip(正芯半导体) · GaN Transistors(GaN HEMT) · TO-252

RC65D270E from RealChip(正芯半导体), in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the normally-off GaN HEMT, driven with VGS 0V to 10V in the datasheet test conditions and rated -20V to +20V (VGSS).
2 S passive Source, the short centre lead, which is also connected to the exposed bottom tab; the package configuration is listed as Source.
3 D passive Drain, rated 650V (VDSS) with 900V transient and 7.9A continuous current at TC=25°C.

Key specifications

Parameter Value
Manufacturer RealChip(正芯半导体)
Package TO-252
Category Gallium Nitride (GaN) Devices
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain to source voltage (TJ = -55°C to 150°C) VDSS 650 V TJ = -55°C to 150°C 2
Drain to source voltage-transient V(TR)DSS 900 V Footnote a: off-state, spike duty cycle D<0.01, spike duration <1μs 2
Gate to source voltage VGSS -20 20 V 2
Continuous drain current @TC=25°C ID 7.9 A TC=25°C; footnote b 2
Continuous drain current @TC=125°C ID 3.5 A TC=125°C; footnote b 2
Pulse drain current IDM 30 A Pulse width 100μs 2
Maximum power dissipation PD 32 W TC=25°C 2
Operating temperature, case TC -55 150 °C 2
Operating temperature, junction TJ -55 150 °C 2
Storage temperature TS -55 150 °C 2
Junction-to-case thermal resistance Rθ J C 3.9 °C /W 3
Drain-source voltage (breakdown) V(BL)DSS 650 V VGS= 0V 4
Drain-source on-resistance RDS(on) 270 320 mΩ VGS=10V, ID=1A, TJ=25°C 4
Drain-to-source leakage current IDSS 10 μA VDS=650V, VGS= 0V, TJ=25°C 4
Drain-to-source leakage current IDSS 100 μA VDS=650V, VGS= 0V, TJ=150°C 4
Gate-to-source forward leakage current IGSS -100 100 nA VGS=±20V 4
Source-Drain reverse voltage VSD 2.2 V VGS=0V, ISD=5A 5
Gate threshold voltage VGS(th) 1.9 V VDS=1V, IDS=1mA 4
Gate threshold voltage temperature coefficient ΔVGS(th)/TJ -7 mV/°C 4
Drain-source on-resistance RDS(on) 570 mΩ VGS=10V, ID=1A, TJ=150°C 4
Input capacitance CISS 243 pF 4
Output capacitance COSS 10 pF VGS=0V, VDS=400V, f=1MHz 4
Reverse capacitance CRSS 0.8 pF 4
Total gate charge QG 7.2 nC 4
Gate-source charge QGS 2.1 nC VDS=400V, VGS=0V to 10V, ID=1A 4
Gate-drain charge QGD 0.9 nC 4
Output charge QOSS 17 nC VGS=0V, VDS=0V to 400V, f=1MHz 4
Turn-on delay tD(on) 6 ns VDS=400V, VGS=0V to 10V, ID=2.1A, RG-on(ext)=6.8Ω, RG-off(ext)=2.2Ω, L=250μH 4
Rise time tR 17 ns 4
Turn-off delay tD(off) 7 ns 4
Fall time tF 15 ns 4
Reverse recovery time tRR 14 ns IF=5A, VDD=400V, dIF/dt=165A/μs 5
Reverse recovery charge QRR 6.5 nC 5

CAD (KiCad official)

  • Symbol: RC65D270E
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: rc65d270e-etched.step / rc65d270e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rc65d270e.step / rc65d270e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RealChip(正芯半导体) datasheet (10 pp, sha256 3d8c65beaf4cd508, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF