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RAA211835GSP#HA0

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RENESAS DC-DC Converters, HTSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)raa211835gsp#ha0factory-2.0.0extractor-text

Verified RAA211835GSP#HA0

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: RAA211835GSP#HA0 · HTSSOP-16 · 17 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 23-page datasheet
  • ✓distributor: lcsc C20353797, digikey 20-RAA211835GSP#HA0TR-ND, mouser 968-RAA211835GSP#HA0
  • ✓family: TSSOP-16-1EP_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0eoe8jc7/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ raa211835gsp-ha0.kicad_sym✓ raa211835gsp-ha0.kicad_mod✓ raa211835gsp-ha0.step
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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers raa211835gsp-ha0: viewers · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
raa211835gsp-ha0-etched.glb Publish 0.1.0 · Ray 7d ago
raa211835gsp-ha0-etched.step raa211835gsp-ha0: factory component page (tier=mfr) · Ray 7d ago
raa211835gsp-ha0-hero.glb raa211835gsp-ha0: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
raa211835gsp-ha0-hero.overlay.json Publish 0.1.0 · Ray 7d ago
raa211835gsp-ha0.glb Publish 0.1.0 · Ray 7d ago
raa211835gsp-ha0.kicad_mod Publish 0.1.0 · Ray 7d ago
raa211835gsp-ha0.kicad_sym Publish 0.1.0 · Ray 7d ago
raa211835gsp-ha0.lbr Publish 0.1.0 · Ray 7d ago
raa211835gsp-ha0.step Publish 0.1.0 · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 7d ago

RAA211835GSP#HA0

RENESAS · DC-DC Converters · HTSSOP-16

RAA211835GSP#HA0 from RENESAS, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground connected to the source of the integrated low-side FET; place input bypass capacitors as close as possible to the PGND and VIN pins.
2 PGND power_in Power ground connected to the source of the integrated low-side FET; place input bypass capacitors as close as possible to the PGND and VIN pins.
3 PGND power_in Power ground connected to the source of the integrated low-side FET; place input bypass capacitors as close as possible to the PGND and VIN pins.
4 VIN power_in Drain of the integrated high-side FET and input of the internal bias linear regulator (4.5V to 75V operating); connect to the input rail and decouple to PGND with input bypass capacitors.
5 EN input Enable pin, high-voltage tolerant (rated -0.3V to 76V) and can be connected directly to VIN.
6 VCC power_out Output of the internal linear regulators providing bias for the IC including the gate driver; connect to ground with a ceramic decoupling capacitor.
7 FS passive Sets the switching frequency from 200kHz to 800kHz with a resistor to ground; connect to VCC for the default 400kHz.
8 PG output Open-drain power-good output that can be pulled up with a resistor to VCC or another rail; recommended pull-up voltage is 3.3V or lower.
9 AGND power_in Analog ground of the IC; connect to the PCB ground plane.
10 FB input Inverting input of the feedback error amplifier (0.8V reference); connect to a resistor divider from VOUT to ground to set the output voltage.
11 SS passive Configures soft-start time with a capacitor to ground; tie to VCC for the default 0.5ms soft-start time.
12 EBIAS power_in Input of the auxiliary internal linear regulator that can be connected to the regulator output to provide bias for the IC (3.3V to 40V operating, 45V absolute max).
13 BST passive Bootstrap circuit supply pin; connect to SW with a capacitor to bias the integrated high-side FET gate driver.
14 SW power_out Output switch node connected to the source of the high-side FET and the selected diode; connect to the inductor and the boot capacitor.
15 SW power_out Output switch node connected to the source of the high-side FET and the selected diode; connect to the inductor and the boot capacitor.
16 SW power_out Output switch node connected to the source of the high-side FET and the selected diode; connect to the inductor and the boot capacitor.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package HTSSOP-16
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 4.5 75 V 7
Quiescent Current Iq 90 200 µA EN = 2V, VFB = 0.825V, VIN = 24V, EBIAS = 3.3V, No Switching 7
Shutdown Current 1 µA 7
VIN UVLO Rising Threshold 3.9 4.25 4.5 V 7
EN Rising Threshold 1.125 1.3 1.375 V 7
Feedback Voltage Reference VFB 0.796 0.8 0.804 V 25°C 7
Feedback Voltage Reference VFB 0.792 0.8 0.808 V -40°C to 125°C 7
Soft-Start Charge Current ISS 3.75 5 6.5 µA 7
Switching Frequency fSW 360 400 440 kHz VFB = 0.8 V, FS = VCC 7
Switching Frequency Range 200 800 kHz 8
Peak Current Limit Threshold IHSOC 5 5.5 A 8
PG Overvoltage Threshold 109 112 115 % % of FB Rising 8
PG Undervoltage Threshold 85 88 91 % % of FB Falling 8
VCC Voltage 3.1 3.3 3.5 V 8
VCC UVLO Rising Threshold 2.75 3 3.15 V 8
EBIAS Operating Voltage 3.3 40 V 8
VIN UVLO Falling Hysteresis 325 mV 7
EN Falling Hysteresis 170 mV 7
EN Deglitch Filter 2.5 µs 7
High-Side FET On-Resistance (HTSSOP) RDS_onh 200 mΩ 7
Internal Soft-Start Time tSS 0.5 ms 7
Soft-Start Pull-Down Resistance RSS 1.1 kΩ 7
Soft-Start Done Threshold 1.2 V 7
Minimum On-Time tON_MIN 96 ns 7
Minimum Off-Time tOFF_MIN 220 ns 7
VFB Undervoltage Threshold 0.4 V 8
Foldback Frequency 50 kHz VFB = 0V 8
Hiccup Time tHICCUP 23 ms 8
Thermal Shutdown Threshold 155 °C 8
Thermal Shutdown Recovery Hysteresis 20 °C 8
PG Hysteresis 3 % % of FB 8
PG Deglitch Filter 4 µs Rising and Falling Edges 8
PG Pull-Down Resistance 65 Ω 8
VCC Output Current Limit 50 mA 8
VCC UVLO Falling Hysteresis 280 mV 8
EBIAS Switchover Rising Threshold 3 V 8
EBIAS Switchover Falling Hysteresis 200 mV 8
Input Voltage (VIN) VIN 4.5 75 V 7
Output Voltage (VOUT) VOUT 0.8 V max is 90% of VIN 7
EBIAS Operating Voltage (EBIAS) EBIAS 3.3 40 V 7
Output Current (IOUT) IOUT 0 3 A 7
Junction Temperature (TJ) TJ -40 125 °C 7
VIN VIN -0.3 76 V 6
EBIAS EBIAS -0.3 45 V 6
EN EN -0.3 76 V 6
SW SW -0.7 V max is VIN + 0.3 6
SW Transient SW -3 V -3 for 15ns; max is VIN + 2 6
BST BST -0.7 V max is SW + 4 6
BST to SW -0.3 4 V 6
All other pins -0.3 4 V 6
Maximum Junction Temperature 150 °C 6
Maximum Storage Temperature Range -65 150 °C 6
ESD Human Body Model 1.5 kV Tested per JS-001-2017 6
ESD Charged Device Model 750 V Tested per JS-002-2018 6
Latch-Up 100 mA Tested per JESD78E; Class 2, Level A 6
Thermal Resistance Junction-Ambient, HTSSOP θJA 35 °C/W JEDEC board, 9 thermal vias under EPAD 6
Thermal Resistance Junction-Ambient on EVB, HTSSOP θJA(EVB) 20.1 °C/W 4-layer evaluation board 6
Thermal Resistance Junction-Case, HTSSOP θJC 3 °C/W case temp at center of exposed pad 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper used, place it as close as possible to the 0.1µF/1µF/10µF capacitors near the VIN pin. 3. Keep the phase node copper area small to reduce parasitic capacitance, but large enough to handle the load 18

CAD (KiCad official)

  • Symbol: RAA211835GSP#HA0
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: raa211835gsp-ha0-etched.step / raa211835gsp-ha0-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); raa211835gsp-ha0.step / raa211835gsp-ha0.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (23 pp, sha256 cba7788b6ceafa84, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF