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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

R7F123FLG4AFB-C#BA0

RENESAS · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

R7F123FLG4AFB-C#BA0 from RENESAS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P120/ANI25/TI07/TO07/TRDIOD0/SO01/INTP4	bidirectional	Port 12 I/O pin (EVDD0 domain) with ANI25 normal-speed A/D input, timer I/O, SO01 output and INTP4 interrupt input; N-ch open-drain output selectable.
2	P43/LRXD0	bidirectional	Port 4 I/O pin with LIN serial data input LRXD0 (via PIOR) and selectable input threshold.
3	P42/LTXD0	bidirectional	Port 4 I/O pin with LIN serial data output LTXD0 (via PIOR).
4	P41/TI10/TO10/TRJIO0/TRD0RES/SNZOUT2	bidirectional	Port 4 I/O pin with timer I/O, timer RJ I/O, timer RDe0 counter clear trigger input and SNOOZE status output; selectable input threshold.
5	P40/TOOL0	bidirectional	Port 4 I/O pin and data I/O for flash programmer/debugger; must be pulled up externally when on-chip debugging is enabled, and EVDD at reset release gives normal mode while 0 V gives flash programming mode.
6	RESET	input	Active-low external system reset input; connect directly or via a resistor to VDD when unused.
7	P124/XT2/EXCLKS	input	Input port pin shared with subsystem clock resonator connection XT2 or external subsystem clock input EXCLKS (do not use XT functions in grade-5 products).
8	P123/XT1	input	Input port pin shared with subsystem clock resonator connection XT1 (do not use in grade-5 products).
9	P137/INTP0	input	Input-only port pin with external interrupt request input INTP0.
10	P122/X2/EXCLK	input	Input port pin shared with main system clock resonator connection X2 or external clock input EXCLK.
11	P121/X1	input	Input port pin shared with main system clock resonator connection X1.
12	REGC	passive	Regulator output stabilization capacitor connection; connect to VSS via a 0.47 to 1 uF capacitor.
13	VSS	power_in	Ground for P33, P34, P80 to P87, P90 to P96, P121 to P124, P137, RESET and non-port pins.
14	EVSS0	power_in	Ground for port pins not connected to VSS.
15	VDD	power_in	Positive supply for P33, P34, P80 to P87, P90 to P96, P121 to P124, P137, RESET and non-port pins; 2.7 V to 5.5 V supply range.
16	EVDD0	power_in	Positive supply for port pins not connected to VDD.
17	P60/TO01/SCK00/SCL00	bidirectional	Port 6 I/O pin (EVDD0) with N-ch open-drain output option and alternate timer/serial functions via PIOR.
18	P61/TO02/SI00/SDA00/RXD0	bidirectional	Port 6 I/O pin with N-ch open-drain output option and alternate timer/serial functions via PIOR.
19	P62/TO03/SO00/TXD0/SCLA0	bidirectional	Port 6 I/O pin with IICA0 clock I/O SCLA0, N-ch open-drain output and TTL input buffer options.
20	P63/TO07/SSI00/SDAA0	bidirectional	Port 6 I/O pin with IICA0 data I/O SDAA0, N-ch open-drain output and TTL input buffer options.
21	P00/TI05/TO05/INTP9	bidirectional	Port 0 I/O pin with external interrupt input INTP9 and timer I/O via PIOR.
22	P140/TRD1RES/PCLBUZ0	bidirectional	Port 14 I/O pin with clock/buzzer output PCLBUZ0 and timer RDe1 counter clear trigger input.
23	P130/RESOUT	output	Output-only port 13 pin with reset output RESOUT.
24	P77/SSI10/INTP12/KR7	bidirectional	Port 7 I/O pin with INTP12 interrupt input and KR7 key interrupt input.
25	P76/SCK10/KR6	bidirectional	Port 7 I/O pin with key interrupt input KR6 and CSI10 clock via PIOR.
26	P75/SI10/RXD1/KR5	bidirectional	Port 7 I/O pin with key interrupt input KR5 and serial input via PIOR.
27	P74/ANI30/SO10/TXD1/KR4	bidirectional	Port 7 pin with ANI30 normal-speed A/D input (analog input after reset), key interrupt KR4 and serial output via PIOR.
28	P73/ANI29/SSI11/SNZOUT7/KR3	bidirectional	Port 7 pin with ANI29 A/D input (analog input after reset), SSI11 slave select, SNOOZE output and KR3.
29	P72/ANI28/SO11/SNZOUT6/KR2	bidirectional	Port 7 pin with ANI28 A/D input (analog input after reset), SO11 output, SNOOZE output and KR2.
30	P71/ANI27/SCK11/SCL11/INTP6/SNZOUT5/KR1	bidirectional	Port 7 pin with ANI27 A/D input (analog input after reset), CSI11/IIC11 clock, INTP6, SNOOZE output and KR1.
31	P70/ANI26/SI11/SDA11/INTP8/SNZOUT4/KR0	bidirectional	Port 7 pin with ANI26 A/D input (analog input after reset), CSI11/IIC11 data, INTP8, SNOOZE output and KR0.
32	P32/SO11/INTP7	bidirectional	Port 3 I/O pin with INTP7 interrupt input and SO11 via PIOR; N-ch open-drain output selectable.
33	P30/TI01/TO01/TRDIOD1/SSI00/INTP2/SNZOUT0	bidirectional	Port 3 I/O pin with timer I/O, SSI00 slave select, INTP2 interrupt and SNOOZE output; TTL input and selectable threshold.
34	P17/TI00/TO00/TRDIOB1/SCK00/SCL00/INTP3	bidirectional	Port 1 I/O pin with timer I/O, CSI00/IIC00 clock and INTP3 interrupt; TTL input and N-ch open-drain options.
35	P16/TI02/TO02/TRDIOC1/SI00/SDA00/RXD0/TOOLRXD	bidirectional	Port 1 I/O pin with serial data input/IIC00 data and TOOLRXD programming UART reception.
36	P15/TI05/TO05/TRDIOA1/SO00/TXD0/RTC1HZ/TOOLTXD	bidirectional	Port 1 I/O pin with serial output, RTC 1 Hz output and TOOLTXD programming UART transmission.
37	P31/INTP2/STOPST	bidirectional	Port 3 I/O pin with STOP status output STOPST.
38	P50/SSI01/INTP3	bidirectional	Port 5 I/O pin with SSI01 slave select and INTP3 via PIOR; selectable input threshold.
39	P51/SO01/INTP11	bidirectional	Port 5 I/O pin with INTP11 interrupt input and SO01 via PIOR.
40	P52/SCK01/STOPST	bidirectional	Port 5 I/O pin with SCK01 and STOPST via PIOR/STPSTC; selectable input threshold.
41	P53/SI01/INTP10	bidirectional	Port 5 I/O pin with INTP10 interrupt input and SI01 via PIOR; selectable input threshold.
42	P14/TI06/TO06/TRDIOC0/SCK01/SCL01/LRXD0	bidirectional	Port 1 I/O pin with timer I/O, CSI01/IIC01 clock and LIN input LRXD0; TTL input and N-ch open-drain options.
43	P13/TI04/TO04/TRDIOA0/TRDCLK0/SI01/SDA01/LTXD0	bidirectional	Port 1 I/O pin with timer I/O, timer RDe clock input, CSI01/IIC01 data and LIN output LTXD0.
44	P12/TI11/TO11/TRDIOD0/SO10/TXD1/INTP5/SNZOUT3	bidirectional	Port 1 I/O pin with timer I/O, serial output, INTP5 interrupt and SNOOZE output; N-ch open-drain option.
45	P11/TI12/TO12/TRDIOB0/SI10/SDA10/RXD1	bidirectional	Port 1 I/O pin with timer I/O and serial data input/IIC10 data; TTL input and N-ch open-drain options.
46	P10/TI13/TO13/TRJO0/SCK10/SCL10	bidirectional	Port 1 I/O pin with timer I/O, timer RJ output and CSI10/IIC10 clock; TTL input and N-ch open-drain options.
47	P33/AVREFP/ANI6	bidirectional	Port 3 pin (VDD domain) with A/D converter positive reference input AVREFP and ANI6 high-speed analog input; analog input mode after reset.
48	P34/AVREFM/ANI7	bidirectional	Port 3 pin (VDD domain) with A/D converter negative reference input AVREFM and ANI7 high-speed analog input; analog input mode after reset.
49	P80/ANI0	bidirectional	Port 8 pin (VDD domain) with ANI0 high-speed A/D input; analog input after reset.
50	P81/ANI1	bidirectional	Port 8 pin (VDD domain) with ANI1 high-speed A/D input; analog input after reset.
51	P82/ANI2	bidirectional	Port 8 pin (VDD domain) with ANI2 high-speed A/D input; analog input after reset.
52	P83/ANI3	bidirectional	Port 8 pin (VDD domain) with ANI3 high-speed A/D input; analog input after reset.
53	P84/ANI4	bidirectional	Port 8 pin (VDD domain) with ANI4 high-speed A/D input; analog input after reset.
54	P85/ANI5	bidirectional	Port 8 pin (VDD domain) with ANI5 high-speed A/D input; analog input after reset.
55	P86/ANI8	bidirectional	Port 8 pin (VDD domain) with ANI8 high-speed A/D input; analog input after reset.
56	P87/ANI9/KR0	bidirectional	Port 8 pin (VDD domain) with ANI9 high-speed A/D input and KR0 via PIOR; analog input after reset.
57	P90/ANI10/KR1	bidirectional	Port 9 pin (VDD domain) with ANI10 high-speed A/D input and KR1 via PIOR; analog input after reset.
58	P91/ANI11/KR2	bidirectional	Port 9 pin (VDD domain) with ANI11 high-speed A/D input and KR2 via PIOR; analog input after reset.
59	P92/ANI12/KR3	bidirectional	Port 9 pin (VDD domain) with ANI12 high-speed A/D input and KR3 via PIOR; analog input after reset.
60	P93/ANI13/KR4	bidirectional	Port 9 pin (VDD domain) with ANI13 high-speed A/D input and KR4 via PIOR; analog input after reset.
61	P94/ANI14/KR5	bidirectional	Port 9 pin (VDD domain) with ANI14 high-speed A/D input and KR5 via PIOR; analog input after reset.
62	P95/ANI15/KR6	bidirectional	Port 9 pin (VDD domain) with ANI15 high-speed A/D input and KR6 via PIOR; analog input after reset.
63	P96/ANI16/KR7	bidirectional	Port 9 pin (VDD domain) with ANI16 normal-speed A/D input and KR7 via PIOR; analog input after reset.
64	P125/ANI24/TI03/TO03/TRDIOB0/SSI01/INTP1/SNZOUT1	bidirectional	Port 12 I/O pin (EVDD0) with ANI24 normal-speed A/D input, timer I/O, SSI01 slave select, INTP1 interrupt and SNOOZE output; analog input after reset.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: R7F123FLG4AFB-C#BA0
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: r7f123flg4afb-c-ba0-etched.step / r7f123flg4afb-c-ba0-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); r7f123flg4afb-c-ba0.step / r7f123flg4afb-c-ba0.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (2045 pp, sha256 98fd96e71eb75fc7, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF