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R5F572MDDDFP#10

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RENESAS Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersr5f572mdddfp#10factory-2.0.0extractor-text
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Contents

README

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R5F572MDDDFP#10

RENESAS · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

R5F572MDDDFP#10 from RENESAS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVSS0 power_in Analog ground pin for the 12-bit A/D converter (unit 0), connected to a branch of the VSS ground supply with a 0.1-µF capacitor to AVCC0.
2 AVCC1 power_in Analog supply and reference voltage for the 12-bit A/D converter (unit 1), the D/A converter and the temperature sensor, connected to a branch of VCC with a 0.1-µF capacitor to AVSS1.
3 AVSS1 power_in Analog ground for the 12-bit A/D converter (unit 1), the D/A converter and the temperature sensor, connected to a branch of VSS with a 0.1-µF capacitor to AVCC1.
4 P00 bidirectional General-purpose I/O port P00 (6-bit port group) multiplexed with TMRI0, TXD6/SMOSI6/SSDA6, AUDIO_CLK, CATLATCH1, IRQ8 and analog input AN118.
5 EMLE input On-chip emulator enable input that must be driven high when the on-chip emulator is used and low when not used.
6 VCL passive Connect to VSS via a 0.22-µF multilayer ceramic capacitor placed close to the pin.
7 VBATT power_in Backup power supply pin, operated at 1.62 to 3.6 V under the sub-clock timing conditions.
8 MD/FINED input Operating-mode select pin whose signal level must not be changed during operation; the same pin serves as the FINE interface (FINED) for on-chip debugging.
9 XCIN input Input pin of the sub-clock oscillator; a crystal resonator is connected between XCOUT and XCIN.
10 XCOUT output Output pin of the sub-clock oscillator; a crystal resonator is connected between XCOUT and XCIN.
11 RES# input Active-low reset input; the MCU enters the reset state while this signal is low.
12 XTAL output Crystal resonator connection for the main clock (8 to 24 MHz); an external clock can instead be input through EXTAL, and the pin also carries port P37.
13 VSS power_in Ground pin, connected to the system power supply at 0 V.
14 EXTAL input External clock input (or crystal connection) for the main clock; external clock input frequency is up to 30 MHz, and the pin also carries port P36.
15 VCC power_in Digital power supply pin for the 2.7 to 3.6 V operating range, decoupled to VSS with a 0.1-µF capacitor placed close to the pin.
16 P35 input Selects the power supply method in USB boot mode (low = self-power, high = bus power); P35 is an input-only port pin and NMI is the non-maskable interrupt request input.
17 P34 input JTAG/boundary-scan reset input, dedicated to the on-chip emulator when EMLE is high; otherwise I/O port P34 with MTU0A, TMCI3, SCK6/SCK0 and IRQ4 functions.
18 P33 bidirectional 5-V tolerant I/O port P33 with MTU0D, TMRI3, EDREQ1 and PCKO functions, RXD6/RXD0 serial inputs and IRQ3-DS, usable as a deep software standby release trigger.
19 P32 bidirectional 5-V tolerant I/O port P32 with MTU0C, TMO3, RTCOUT, TXD6/TXD0, CTX0, USB0_VBUSEN and VSYNC functions and IRQ2-DS.
20 P31 input JTAG TMS input when the on-chip emulator is enabled; otherwise 5-V tolerant I/O port P31 with MTU4D, TMCI2, RTCIC1, CTS1#/RTS1#/SS1# and IRQ1-DS functions.
21 P30 input JTAG TDI input when the on-chip emulator is enabled; otherwise 5-V tolerant I/O port P30 with MTU4B, TMRI3, RTCIC0, RXD1/SMISO1 and IRQ0-DS functions.
22 P27 input JTAG TCK input when the on-chip emulator is enabled; otherwise I/O port P27 with MTU2B, TMCI3, SCK1/RSPCKB-A and ET1_WOL/CATIRQ functions.
23 P26 output JTAG TDO output when the on-chip emulator is enabled; otherwise I/O port P26 with MTU2A, TMO1, TXD1/SMOSI1, CTS3#/RTS3#/SS3# and MOSIB-A functions.
24 P25 output Clock output pin CLKOUT (cycle time at least 25 ns per the CLKOUT timing table), sharing the pin with I/O port P25 that also carries MTU4C, RXD3/SMISO3 and ADTRG0#.
25 P24 bidirectional I/O port P24 with MTU4A, MTCLKA, TIOCB4, TMRI1, SCK3, USB0_VBUSEN and SSIBCK1 functions.
26 P23 bidirectional I/O port P23 with MTU3D, MTCLKD, TIOCD3, GPTW GTIOC0A, TXD3/SMOSI3, CTS0#/RTS0#/SS0#, CTX1 and SSIBCK0 functions.
27 P21 bidirectional I/O port P21 with MTU1B, MTU4A, TMCI0, GPTW GTIOC2A, RXD0/SMISO0, USB0_EXICEN, SSILRCK0 and IRQ9 functions.
28 P20 bidirectional I/O port P20 with MTU1A, TIOCB3, TMRI0, TXD0/SMOSI0, SDA1, USB0_ID, SSIRXD0 and IRQ8 functions.
29 P17 bidirectional 5-V tolerant I/O port P17 with MTU3A, MTU3B, MTU4B, GPTW GTIOC0B, TMO1, SCI1/SCI3 SCK1/TXD3, SDA2-DS, SSITXD0, IRQ7 and ADTRG1# functions.
30 P87 bidirectional I/O port P87 with MTU4C, TIOCA2, GPTW GTIOC1B, SMOSI10/SSDA10/TXD10, and EPLSOUT1/CATSYNC1 functions.
31 P16 bidirectional 5-V tolerant I/O port P16 with MTU3C, MTU3D, TIOCB1, TMO2, TXD1/SMOSI1, RXD3/SMISO3, USB0_VBUSEN, USB0_VBUS, USB0_OVRCURB, IRQ6 and ADTRG0# functions.
32 P86 bidirectional I/O port P86 with MTU4D, TIOCA0, GPTW GTIOC2B, SMISO10/SSCL10/RXD10 and CATLINKACT0 functions.
33 P15 bidirectional 5-V tolerant I/O port P15 with MTU0B, MTCLKB, TIOCB2, TCLKB, TMCI2, GPTW GTETRGA, RXD1/SMISO1, SCK3, CRX1-DS, SSILRCK1, CATLEDRUN, PIXD0 and IRQ5 functions.
34 P14 bidirectional I/O port P14 with MTU3A, MTCLKA, TIOCB5, TCLKA, TMRI2, GPTW GTETRGD, CTS1#/RTS1#/SS1#, CTX1, USB0_OVRCURA and IRQ4 functions.
35 VCC_USB power_in Power supply pin for the USB module, which must be connected to VCC.
36 USB0_DM bidirectional USB 2.0 full-speed transceiver D- data pin.
37 USB0_DP bidirectional USB 2.0 full-speed transceiver D+ data pin.
38 VSS_USB power_in Ground pin for the USB module, which must be connected to VSS.
39 P56 output 25-MHz clock output for the PHY clock input (shared with EtherCAT), sharing the pin with I/O port P56 that also carries MTU3C, TIOCA1 and SCK7 functions.
40 P51 bidirectional I/O port P51 with SCK2 and SSLB2-A functions.
41 P52 bidirectional I/O port P52 with RXD2/SMISO2/SSCL2, SSLB3-A and CATLEDSTER functions.
42 P50 bidirectional I/O port P50 with TXD2/SMOSI2/SSDA2, SSLB1-A and CATLEDERR functions.
43 VSS power_in Ground pin, connected to the system power supply at 0 V.
44 VCC power_in Digital power supply pin for the 2.7 to 3.6 V operating range, decoupled to VSS with a 0.1-µF capacitor placed close to the pin.
45 PC7 input USB boot mode enable input (UB), sharing the pin with I/O port PC7 that also carries MTU3A, GPTW GTIOC3A, TXD8, ET0_COL and IRQ14 functions.
46 PC6 bidirectional I/O port PC6 with MTU3C, MTCLKA, TMCI2, GPTW GTIOC3B, RXD8/SMISO8, ET0_ETXD3/CAT0_ETXD3, CATLATCH1 and IRQ13 functions.
47 PC5 bidirectional I/O port PC5 with MTU3B, MTCLKD, TMRI2, GPTW GTIOC1A, SCK8/RTS8#/SCK10 and ET0_ETXD2/CAT0_ETXD2 functions.
48 P82 bidirectional I/O port P82 with MTU4A, PO28, GPTW GTIOC2A, SMOSI10/SSDA10/TXD10, ET0_ETXD1/RMII0_TXD1, CAT0_ETXD1 and CATI2CDATA functions.
49 P81 bidirectional I/O port P81 with MTU3D, PO27, GPTW GTIOC0B, SMISO10/SSCL10/RXD10, ET0_ETXD0/RMII0_TXD0, CAT0_ETXD0 and CATI2CCLK functions.
50 P80 bidirectional I/O port P80 with MTU3B, PO26, SCK10/RTS10#, ET0_TX_EN/RMII0_TXD_EN, CAT0_TX_EN and CATLATCH0 functions.
51 PC4 bidirectional I/O port PC4 with MTU3D, MTCLKC, TMCI1, PO25, POE0#, GPTW GTETRGC, SCK5, SS8#/CTS8#/SS10#/CTS10#/RTS10#, ET0_TX_CLK/CAT0_TX_CLK and CATSYNC0 functions.
52 PC2 bidirectional 5-V tolerant I/O port PC2 with MTU4B, TCLKA, PO21, GPTW GTIOC2B, RXD5/SMISO5/SSCL5 and ET0_RX_DV/CAT0_RX_DV functions.
53 PB7 bidirectional I/O port PB7 with MTU3B, TIOCB5, PO31, TXD9/SMOSI9/SSDA9, SMOSI11/SSDA11/TXD11, and ET0_CRS/RMII0_CRS_DV/CAT0_RX_DV functions.
54 PB6 bidirectional I/O port PB6 with MTU3D, TIOCA5, PO30, RXD9/SMISO9/SSCL9, SMISO11/SSCL11/RXD11, and ET0_ETXD1/RMII0_TXD1/CAT0_ETXD1 functions.
55 PB5 bidirectional I/O port PB5 with MTU2A, MTU1B, TIOCB4, TMRI1, PO29, POE4#, SCK9/RTS9#/SCK11 and ET0_ETXD0/RMII0_TXD0/CAT0_ETXD0 functions.
56 PB4 bidirectional I/O port PB4 with TIOCA4, PO28, SS9#/CTS9#/SS11#/CTS11#/RTS11#, and ET0_TX_EN/RMII0_TXD_EN/CAT0_TX_EN functions.
57 PB3 bidirectional I/O port PB3 with MTU0A, MTU4A, TIOCD3, TCLKD, TMO0, PO27, POE11#, SCK4/SCK6 and ET0_RX_ER/RMII0_RX_ER/CAT0_RX_ER functions.
58 PB1 bidirectional I/O port PB1 with MTU0C, MTU4C, TIOCB3, TMCI0, PO25, TXD4/SMOSI4, TXD6/SMOSI6, ET0_ERXD0/RMII0_RXD0/CAT0_ERXD0 and IRQ4-DS functions.
59 PB0 bidirectional I/O port PB0 with MTIC5W, TIOCA3, PO24, RXD4/SMISO4, RXD6/SMISO6, ET0_ERXD1/RMII0_RXD1/CAT0_ERXD1 and IRQ12 functions.
60 PA6 bidirectional I/O port PA6 with MTIC5V, MTCLKB, TIOCA2, TMCI3, PO22, POE10#, GPTW GTETRGB, CTS5#/RTS5#/SS5#, and ET0_EXOUT/CATRESTOUT functions.
61 VCC power_in Digital power supply pin for the 2.7 to 3.6 V operating range, decoupled to VSS with a 0.1-µF capacitor placed close to the pin.
62 PA4 bidirectional I/O port PA4 with MTIC5U, MTCLKA, TIOCA1, TMRI0, PO20, TXD5/SMOSI5/SSDA5, ET0_MDC/CAT0_MDC/CATIRQ/PMGI0_MDC and IRQ5-DS functions.
63 VSS power_in Ground pin, connected to the system power supply at 0 V.
64 PA3 bidirectional I/O port PA3 with MTU0D, MTCLKD, TIOCD0, TCLKB, PO19, RXD5/SMISO5/SSCL5, ET0_MDIO/CAT0_MDIO/PMGI0_MDIO and IRQ6-DS functions.
65 PA2 bidirectional I/O port PA2 with MTU7A, PO18, GPTW GTIOC1A, RXD5/SMISO5/SSCL5 and CATLINKACT1 functions.
66 PG6 bidirectional I/O port PG6 with ET1_ETXD3/CAT1_ETXD3 Ethernet/EtherCAT transmit data functions.
67 PA1 bidirectional I/O port PA1 with MTU0B, MTCLKC, MTU7B, TIOCB0, PO17, GPTW GTIOC2A, SCK5, ET0_WOL and IRQ11 functions.
68 PG5 bidirectional I/O port PG5 with ET1_ETXD2/CAT1_ETXD2 Ethernet/EtherCAT transmit data functions.
69 PA0 bidirectional I/O port PA0 with MTU4A, MTU6D, TIOCA0, PO16, CACREF, GPTW GTIOC0B, ET0_TX_EN/RMII0_TXD_EN/CAT0_TX_EN and CATLEDRUN functions.
70 P67 bidirectional 5-V tolerant I/O port P67 with MTU7C, GPTW GTIOC1B, CRX2, EPLSOUT1/CATSYNC1 and IRQ15 functions.
71 P66 bidirectional I/O port P66 with MTU7D, GPTW GTIOC2B and CTX2 functions.
72 PG2 bidirectional I/O port PG2 with ET1_TX_CLK/CAT1_TX_CLK Ethernet/EtherCAT clock functions.
73 PE5 bidirectional I/O port PE5 with MTU4C, MTU2B, GPTW GTIOC0A, RSPCKB-B, ET0_RX_CLK/REF50CK0/CAT0_RX_CLK, IRQ5 and analog input AN103.
74 PE4 bidirectional I/O port PE4 with MTU4D, MTU1A, PO28, GPTW GTIOC1A, ET0_ERXD2/CAT0_ERXD2 and analog input AN102.
75 PE3 bidirectional I/O port PE3 with MTU4B, PO26, TOC3, POE8#, GPTW GTIOC2A, ET0_ERXD3/CAT0_ERXD3 and analog input AN101.
76 P64 bidirectional I/O port P64 with ET1_ETXD0/RMII1_TXD0/CAT1_ETXD0 Ethernet/EtherCAT transmit data functions.
77 P63 bidirectional I/O port P63 with ET1_ETXD1/RMII1_TXD1/CAT1_ETXD1 Ethernet/EtherCAT transmit data functions.
78 P62 bidirectional I/O port P62 with ET1_ERXD0/RMII1_RXD0/CAT1_ERXD0 Ethernet/EtherCAT receive data functions.
79 P61 bidirectional I/O port P61 with ET1_ERXD1/RMII1_RXD1/CAT1_ERXD1 Ethernet/EtherCAT receive data functions.
80 VSS power_in Ground pin, connected to the system power supply at 0 V.
81 P60 bidirectional I/O port P60 with ET1_TX_EN/RMII1_TXD_EN/CAT1_TX_EN transmit enable functions.
82 VCC power_in Digital power supply pin for the 2.7 to 3.6 V operating range, decoupled to VSS with a 0.1-µF capacitor placed close to the pin.
83 PD7 bidirectional I/O port PD7 with MTIC5U, POE0#, ET1_RX_ER/RMII1_RX_ER/CAT1_RX_ER, IRQ7 and analog input AN107.
84 PD6 bidirectional I/O port PD6 with MTIC5V, MTIOC8A, POE4#, ET1_RX_CLK/REF50CK1/CAT1_RX_CLK, IRQ6 and analog input AN106.
85 P97 bidirectional I/O port P97 with ET1_ERXD3/CAT1_ERXD3 Ethernet/EtherCAT receive data functions.
86 P96 bidirectional I/O port P96 with ET1_ERXD2/CAT1_ERXD2 Ethernet/EtherCAT receive data functions.
87 PD2 bidirectional I/O port PD2 with MTU4D, TIC2, GPTW GTIOC0B, CRX0, ET1_EXOUT, IRQ2 and analog input AN110.
88 PD1 bidirectional I/O port PD1 with MTU4B, POE0#, GPTW GTIOC1A, CTX0, IRQ1 and analog input AN109.
89 P93 bidirectional I/O port P93 with POE0#, CTS7#/RTS7#/SS7#, ET1_LINKSTA/CAT1_LINKSTA and analog input AN117.
90 P92 bidirectional I/O port P92 with POE4#, RXD7/SMISO7/SSCL7, ET1_CRS/RMII1_CRS_DV/CAT1_RX_DV and analog input AN116.
91 P91 bidirectional I/O port P91 with SCK7, ET1_COL and analog input AN115.
92 VSS power_in Ground pin, connected to the system power supply at 0 V.
93 P90 bidirectional I/O port P90 with TXD7/SMOSI7/SSDA7, ET1_RX_DV/CAT1_RX_DV and analog input AN114.
94 VCC power_in Digital power supply pin for the 2.7 to 3.6 V operating range, decoupled to VSS with a 0.1-µF capacitor placed close to the pin.
95 P42 bidirectional I/O port P42 with IRQ10-DS (deep software standby release trigger) and analog input AN002.
96 P41 bidirectional I/O port P41 with IRQ9-DS (deep software standby release trigger) and analog input AN001.
97 VREFL0 power_in Analog reference ground for the 12-bit A/D converter (unit 0); connect to VSS if the A/D converter is not used.
98 P40 bidirectional I/O port P40 with IRQ8-DS (deep software standby release trigger) and analog input AN000.
99 VREFH0 power_in Analog reference voltage for the 12-bit A/D converter (unit 0); connect to VCC if the A/D converter is not used.
100 AVCC0 power_in Analog supply voltage for the 12-bit A/D converter (unit 0), connected to a branch of VCC with a 0.1-µF capacitor to AVSS0.

Key specifications

Parameter Value
Manufacturer RENESAS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VCC, VCC_USB VCC -0.3 4 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
VBATT power supply voltage VBATT -0.3 4 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
Input voltage except 5 V tolerant ports (max printed as VCC + 0.3, up to 4.0 V) Vin -0.3 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
Input voltage 5 V tolerant ports (max printed as VCC + 4.0, up to 5.8 V) Vin -0.3 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
Reference power supply voltage VREFH0 (max printed as AVCC0 + 0.3, up to 4.0 V) VREFH0 -0.3 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
Analog power supply voltage AVCC0, AVCC1 AVCC0, AVCC1 -0.3 4 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
Analog input voltage (max printed as AVCC + 0.3, up to 4.0 V) VAN -0.3 V VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V 81
Junction temperature, D version Tj -40 105 °C D version 81
Junction temperature, G version Tj -40 125 °C G version 81
Storage temperature Tstg -55 125 °C 81
Power supply voltage VCC VCC 2.7 3.6 V 82
VBATT power supply voltage VBATT 1.62 3.6 V 82
Reference power supply voltage VREFH0 (max printed as AVCC0) VREFH0 2.7 V 82
Input voltage except 5 V tolerant ports (max printed as VCC + 0.3) Vin -0.3 V 82
Input voltage ports P03, P05, P40-P47 (max printed as AVCC0 + 0.3) Vin -0.3 V 82
Input voltage 5 V tolerant ports P11-P17, P20, P21, P30-P33, P67, PC0-PC3 (max printed as VCC + 3.6, up to 5.5 V) Vin -0.3 V 82
Input voltage 5 V tolerant port P07 (max printed as AVCC0 + 3.6, up to 5.5 V) Vin -0.3 V 82
Operating temperature, D version Topr -40 85 °C D version 82
Operating temperature, G version Topr -40 105 °C G version 82
Decoupling capacitance for stabilizing the internal voltage CVCL 0.22 µF 82
Decoupling capacitance CVCL tolerance CVCL -30 30 % Sum of capacitance tolerance and change under usage conditions 82
Output low voltage, all output pins except RIIC and ETHERC VOL 0.5 V IOL = 1.0 mA 84
RIIC output low voltage VOL 0.4 V IOL = 3.0 mA 84
RIIC output low voltage VOL 0.6 V IOL = 6.0 mA 84
RIIC output low voltage, P12 and P13 in channel 0 VOL 0.4 V IOL = 15.0 mA (ICFER.FMPE = 1) 84
ETHERC output low voltage VOL 0.4 V IOL = 1.0 mA 84
Input leakage current RES#, MD, EMLE, BSCANP, NMI /Iin/ 1 µA Vin = 0 V; Vin = VCC 84
Three-state leakage current (off state), other than 5 V tolerant ports /ITSI/ 1 µA Vin = 0 V; Vin = VCC 84
Three-state leakage current (off state), 5 V tolerant ports /ITSI/ 5 µA Vin = 0 V; Vin = 5.5 V 84
Input pull-up resistor current, other than P35 Ip -300 -10 µA VCC = 2.7 to 3.6 V, Vin = 0 V 84
Input pull-down resistor current, EMLE and BSCANP Ip 10 300 µA Vin = VCC 84
Input capacitance, all input pins except P03, P05, P12, P13, P16, P17, P20, P21, EMLE, BSCANP, USB0_DP, USB0_DM Cin 8 pF Vbias = 0 V, Vamp = 20 mV, f = 1 MHz, Ta = 25°C 84
Input capacitance, P03, P05, P12, P13, P16, P17, P20, P21, EMLE, BSCANP, USB0_DP, USB0_DM Cin 16 pF Vbias = 0 V, Vamp = 20 mV, f = 1 MHz, Ta = 25°C 84
Supply current, high-speed full operation, D version ICC 261 mA ICLK = 240 MHz, PCLKA = 120 MHz, PCLKB/PCLKC/PCLKD/FCLK = 60 MHz, BCLK = 120 MHz, BCLK pin = 60 MHz 85
Supply current, high-speed full operation, G version ICC 319 mA ICLK = 240 MHz, PCLKA = 120 MHz, PCLKB/PCLKC/PCLKD/FCLK = 60 MHz, BCLK = 120 MHz, BCLK pin = 60 MHz 85
Supply current, sleep mode, D version ICC 42 144 mA Sleep mode: peripheral module clocks supplied 85
Supply current, sleep mode, G version ICC 42 196 mA Sleep mode: peripheral module clocks supplied 85
Supply current increase by Trusted Secure IP operation, D and G versions ICC 15 mA Increased by Trusted Secure IP operation 85
Deep software standby, power supplied to standby RAM and USB resume detecting unit, D version ICC 15.5 70 µA Deep software standby mode; power supplied to standby RAM and USB resume detecting unit 85
Deep software standby, power supplied to standby RAM and USB resume detecting unit, G version ICC 15.5 98 µA Deep software standby mode; power supplied to standby RAM and USB resume detecting unit 85
Deep software standby, power not supplied to standby RAM, low power consumption function of POR circuit disabled, D version ICC 11.5 42 µA Deep software standby mode; DEEPCUT[1:0] = 01b 85
Deep software standby, power not supplied to standby RAM, low power consumption function of POR circuit disabled, G version ICC 11.5 58 µA Deep software standby mode; DEEPCUT[1:0] = 01b 85
Deep software standby, power not supplied to standby RAM, low power consumption function of POR circuit enabled, D version ICC 4.9 32 µA Deep software standby mode; DEEPCUT[1:0] = 11b 85
Deep software standby, power not supplied to standby RAM, low power consumption function of POR circuit enabled, G version ICC 4.9 47 µA Deep software standby mode; DEEPCUT[1:0] = 11b 85
Inrush current on returning from deep software standby mode, D and G versions (reference value) IRUSH 211 mA Returning from deep software standby mode 85
During 12-bit A/D conversion (unit 0), D and G versions AICC 0.8 1 mA IAVCC0_AD 86
Reference power supply current during 12-bit A/D conversion (unit 0), D and G versions AIREFH 38 60 µA IVREFH0 86
USB operating current, low speed, USB0, D and G versions ICCUSBLS 3.7 6.5 mA VCC_USB 86
RAM retention voltage VRAM 2.7 V 86
Permissible output low current, average value per pin, normal drive IOL 2 mA Normal drive (All output pins, note 1) 87
Permissible output low current, max value per pin, normal drive IOL 4 mA Normal drive (All output pins, note 1) 87
Permissible output low current, total of all output pins ΣIOL 80 mA Total of all output pins 87
Permissible output high current, average value per pin, normal drive IOH -2 mA Normal drive (All output pins, note 1) 87
Permissible output high current, max value per pin, normal drive IOH -4 mA Normal drive (All output pins, note 1) 87
Permissible output high current, total of all output pins ΣIOH -80 mA Total of all output pins 87
Thermal resistance, junction to ambient, 100-pin LFQFP (PLQP0100KB-B) θja 34 °C/W JESD51-2 and JESD51-7 compliant 87
Thermal resistance, junction to case (top), 100-pin LFQFP (PLQP0100KB-B) θjt 0.6 °C/W JESD51-2 and JESD51-7 compliant 87
Operating frequency, system clock (ICLK) f 240 MHz High-speed operating mode 88
Operating frequency, peripheral module clock (PCLKA) 120 MHz High-speed operating mode 88
Operating frequency, external bus clock (BCLK) 120 MHz High-speed operating mode 88

CAD (KiCad official)

  • Symbol: R5F572MDDDFP#10
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: r5f572mdddfp-10-etched.step / r5f572mdddfp-10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); r5f572mdddfp-10.step / r5f572mdddfp-10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (180 pp, sha256 fed2a5dff3630a8c, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF