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R5F10PLJCLFB#15

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RENESAS Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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R5F10PLJCLFB#15

RENESAS · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

R5F10PLJCLFB#15 from RENESAS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P120/ANI25/TI07/TO07/TRDIOD0/SO01/INTP4 bidirectional Port 12 I/O (EVDD0 domain) with ANI25 analog input, TI07/TO07 timer, TRDIOD0 timer RD I/O, SO01 CSI01 data output and INTP4 interrupt input.
2 P43/(LRXD0) bidirectional Port 4 I/O with threshold level selectable; LIN0 serial data input LRXD0 via PIOR redirection.
3 P42/(LTXD0) bidirectional Port 4 I/O; LIN0 serial data output LTXD0 via PIOR redirection.
4 P41/TI10/TO10/TRJIO0/VCOUT0/SNZOUT2 bidirectional Port 4 I/O with timer TI10/TO10, timer RJ I/O TRJIO0, comparator output VCOUT0 and SNOOZE status output SNZOUT2.
5 P40/TOOL0 bidirectional Port 4 I/O and data I/O for flash programmer/debugger; must be pulled up externally to EVDD when on-chip debugging is enabled, 0 V at reset release selects flash programming mode.
6 RESET input Active-low system reset input; connect directly or via a resistor to VDD when unused.
7 P124/XT2/EXCLKS input Input port, subsystem clock resonator connection XT2 or external subsystem clock input EXCLKS (do not use XT1/XT2 in grade-Y products).
8 P123/XT1 input Input port and subsystem clock resonator connection XT1 (do not use in grade-Y products).
9 P137/INTP0 input Input-only port 13 pin with INTP0 external interrupt input (VDD domain).
10 P122/X2/EXCLK input Input port, main system clock resonator connection X2 or external clock input EXCLK.
11 P121/X1 input Input port and main system clock resonator connection X1.
12 REGC passive Regulator output stabilization capacitor connection; connect to VSS via a 0.47 to 1 µF capacitor.
13 VSS power_in Ground potential for P33, P34, P80 to P87, P90 to P96, P121 to P124, P137, RESET and non-port pins.
14 EVSS0 power_in Ground potential for port pins not connected to VSS.
15 VDD power_in Positive supply for P33, P34, P80 to P87, P90 to P96, P121 to P124, P137, RESET and non-port pins; supply range 2.7 V to 5.5 V.
16 EVDD0 power_in Positive supply for port pins not connected to VDD.
17 P60/(SCK00)/(SCL00) bidirectional Port 6 I/O with N-ch open-drain output option; CSI00 clock or simplified I2C clock SCL00 via PIOR.
18 P61/(SI00)/(SDA00)/(RXD0) bidirectional Port 6 I/O with N-ch open-drain output option; SI00, SDA00 or RXD0 via PIOR.
19 P62/(SO00)/(TXD0)/SCLA0 bidirectional Port 6 I/O with N-ch open-drain option; IICA0 clock SCLA0, SO00/TXD0 via PIOR.
20 P63/(SSI00)/SDAA0 bidirectional Port 6 I/O with N-ch open-drain option; IICA0 data SDAA0, SSI00 via PIOR.
21 P00/(TI05)/(TO05)/INTP9 bidirectional Port 0 I/O with INTP9 interrupt input; TI05/TO05 via PIOR.
22 P140/PCLBUZ0 bidirectional Port 14 I/O with clock/buzzer output PCLBUZ0.
23 P130/RESOUT output Port 13 output pin with reset output RESOUT.
24 P77/KR7/(SSI10)/INTP12 bidirectional Port 7 I/O with key interrupt KR7, INTP12 interrupt input and SSI10 via PIOR.
25 P76/KR6/(SCK10) bidirectional Port 7 I/O with key interrupt KR6; CSI10 clock SCK10 via PIOR.
26 P75/KR5/(SI10)/(RXD1) bidirectional Port 7 I/O with key interrupt KR5; SI10/RXD1 via PIOR.
27 P74/KR4/(SO10)/(TXD1) bidirectional Port 7 I/O with key interrupt KR4; SO10/TXD1 via PIOR.
28 P73/KR3/(CRXD0)/SSI11/SNZOUT7 bidirectional Port 7 I/O with key interrupt KR3, SSI11, SNOOZE output SNZOUT7 and CAN input CRXD0 via PIOR.
29 P72/KR2/(CTXD0)/SO11/SNZOUT6 bidirectional Port 7 I/O with N-ch open-drain option, key interrupt KR2, SO11, SNZOUT6 and CAN output CTXD0 via PIOR.
30 P71/KR1/TI17/TO17/INTP6/SCK11/SCL11/SNZOUT5 bidirectional Port 7 I/O with KR1, timer TI17/TO17, INTP6, CSI11 clock SCK11/SCL11 and SNZOUT5.
31 P70/ANI26/KR0/TI15/TO15/INTP8/SI11/SDA11/SNZOUT4 bidirectional Port 7 I/O with ANI26 analog input, KR0, TI15/TO15, INTP8, SI11/SDA11 and SNZOUT4.
32 P32/TI16/TO16/INTP7 bidirectional Port 3 I/O with timer TI16/TO16 and INTP7 interrupt input.
33 P30/TI01/TO01/TRDIOD1/SSI00/INTP2/SNZOUT0 bidirectional Port 3 I/O with TI01/TO01, TRDIOD1, SSI00, INTP2 and SNZOUT0; TTL input buffer selectable.
34 P17/TI00/TO00/TRDIOB1/SCK00/SCL00/INTP3 bidirectional Port 1 I/O with TI00/TO00, TRDIOB1, SCK00/SCL00 and INTP3.
35 P16/TI02/TO02/TRDIOC1/SI00/SDA00/RXD0/TOOLRXD bidirectional Port 1 I/O with TI02/TO02, TRDIOC1, SI00/SDA00, RXD0 and programming UART receive TOOLRXD.
36 P15/TI05/TO05/TRDIOA1/(TRDIOA0)/(TRDCLK0)/SO00/TXD0/TOOLTXD/RTC1HZ bidirectional Port 1 I/O with TI05/TO05, TRDIOA1, SO00/TXD0, programming UART transmit TOOLTXD and RTC1HZ output.
37 P31/TI14/TO14/STOPST/(INTP2) bidirectional Port 3 I/O with TI14/TO14 timer, STOP status output STOPST and INTP2 via PIOR.
38 P50/(SSI01)/(INTP3) bidirectional Port 5 I/O; SSI01 and INTP3 via PIOR.
39 P51/(SO01)/INTP11 bidirectional Port 5 I/O with INTP11 interrupt input; SO01 via PIOR.
40 P52/(SCK01)/(STOPST) bidirectional Port 5 I/O; SCK01 via PIOR and STOPST via STPSTC.
41 P53/(SI01)/INTP10 bidirectional Port 5 I/O with INTP10 interrupt input; SI01 via PIOR.
42 P14/TI06/TO06/TRDIOC0/SCK01/SCL01/LRXD0 bidirectional Port 1 I/O with TI06/TO06, TRDIOC0, SCK01/SCL01 and LIN input LRXD0.
43 P13/TI04/TO04/TRDIOA0/TRDCLK0/SI01/SDA01/LTXD0 bidirectional Port 1 I/O with TI04/TO04, TRDIOA0/TRDCLK0, SI01/SDA01 and LIN output LTXD0.
44 P12/TI11/TO11/(TRDIOD0)/INTP5/SO10/TXD1/SNZOUT3 bidirectional Port 1 I/O with TI11/TO11, INTP5, SO10/TXD1 and SNZOUT3.
45 P11/TI12/TO12/(TRDIOB0)/SI10/SDA10/RXD1/LRXD1/CRXD0 bidirectional Port 1 I/O with TI12/TO12, SI10/SDA10, RXD1 and CAN input CRXD0.
46 P10/TI13/TO13/TRJO0/SCK10/SCL10/LTXD1/CTXD0 bidirectional Port 1 I/O with TI13/TO13, timer RJ output TRJO0, SCK10/SCL10 and CAN output CTXD0.
47 P33/AVREFP/ANI0 bidirectional Port 3 pin (VDD domain) with A/D converter positive reference input AVREFP and analog input ANI0.
48 P34/AVREFM/ANI1 bidirectional Port 3 pin (VDD domain) with A/D converter negative reference input AVREFM and analog input ANI1.
49 P80/ANI2/ANO0 bidirectional Port 8 I/O (VDD domain) with ANI2 analog input and D/A converter output ANO0.
50 P81/ANI3/IVCMP00 bidirectional Port 8 I/O with ANI3 analog input and comparator input IVCMP00.
51 P82/ANI4/IVCMP01 bidirectional Port 8 I/O with ANI4 analog input and comparator input IVCMP01.
52 P83/ANI5/IVCMP02 bidirectional Port 8 I/O with ANI5 analog input and comparator input IVCMP02.
53 P84/ANI6/IVCMP03 bidirectional Port 8 I/O with ANI6 analog input and comparator input IVCMP03.
54 P85/ANI7/IVREF0 bidirectional Port 8 I/O with ANI7 analog input and comparator reference input IVREF0.
55 P86/ANI8 bidirectional Port 8 I/O with ANI8 analog input.
56 P87/ANI9/(KR0) bidirectional Port 8 I/O with ANI9 analog input; KR0 via PIOR.
57 P90/ANI10/(KR1) bidirectional Port 9 I/O with ANI10 analog input; KR1 via PIOR.
58 P91/ANI11/(KR2) bidirectional Port 9 I/O with ANI11 analog input; KR2 via PIOR.
59 P92/ANI12/(KR3) bidirectional Port 9 I/O with ANI12 analog input; KR3 via PIOR.
60 P93/ANI13/(KR4) bidirectional Port 9 I/O with ANI13 analog input; KR4 via PIOR.
61 P94/ANI14/(KR5) bidirectional Port 9 I/O with ANI14 analog input; KR5 via PIOR.
62 P95/ANI15/(KR6) bidirectional Port 9 I/O with ANI15 analog input; KR6 via PIOR.
63 P96/ANI16/(KR7) bidirectional Port 9 I/O with ANI16 analog input in R5F10PLJ; KR7 via PIOR; powered from VDD in this device.
64 P125/ANI24/TI03/TO03/TRDIOB0/SSI01/INTP1/SNZOUT1 bidirectional Port 12 I/O with ANI24 analog input, TI03/TO03, TRDIOB0, SSI01, INTP1 and SNZOUT1.

Key specifications

Parameter Value
Manufacturer RENESAS
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: R5F10PLJCLFB#15
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: r5f10pljclfb-15-etched.step / r5f10pljclfb-15-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); r5f10pljclfb-15.step / r5f10pljclfb-15.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (1879 pp, sha256 737b915299275df9, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF