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R5F100PLAFB#10

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RENESAS Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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R5F100PLAFB#10

RENESAS · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

R5F100PLAFB#10 from RENESAS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P142/SCK30/SCL30 bidirectional Port 14 bit 2 with serial clock I/O (SCK30) or serial clock output (SCL30) for channel 30.
2 P141/PCLBUZ1/INTP7 bidirectional Port 14 bit 1 with programmable clock/buzzer output 1 and external interrupt INTP7.
3 P140/PCLBUZ0/INTP6 bidirectional Port 14 bit 0 with programmable clock/buzzer output 0 and external interrupt INTP6.
4 P120/ANI19 bidirectional Port 12 bit 0 with A/D converter analog input ANI19.
5 P47/INTP2 bidirectional Port 4 bit 7 with external interrupt INTP2.
6 P46/INTP1/TI05/TO05 bidirectional Port 4 bit 6 with external interrupt INTP1 and timer input TI05/output TO05.
7 P45/SO01 bidirectional Port 4 bit 5 with serial data output SO01.
8 P44/SI01/SDA01 bidirectional Port 4 bit 4 with serial data input SI01 or serial data I/O SDA01.
9 P43/SCK01/SCL01 bidirectional Port 4 bit 3 with serial clock I/O SCK01 or serial clock output SCL01.
10 P42/TI04/TO04 bidirectional Port 4 bit 2 with timer input TI04 and timer output TO04.
11 P41 bidirectional Port 4 bit 1 general-purpose I/O.
12 P40/TOOL0 bidirectional Port 4 bit 0 with data I/O for flash programming/on-chip debugger tool (TOOL0).
13 RESET input Active-low external reset input.
14 P124/XT2/EXCLKS bidirectional Port 12 bit 4 with subsystem clock crystal connection XT2 or external subsystem clock input EXCLKS.
15 P123/XT1 bidirectional Port 12 bit 3 with subsystem clock crystal connection XT1.
16 P137/INTP0 input Port 13 bit 7 (input only) with external interrupt INTP0.
17 P122/X2/EXCLK bidirectional Port 12 bit 2 with main clock crystal connection X2 or external clock input EXCLK.
18 P121/X1 bidirectional Port 12 bit 1 with main clock crystal connection X1.
19 REGC passive Regulator capacitance pin; connect to VSS via a capacitor (0.47 to 1 µF).
20 VSS power_in Ground; EVSS0 and EVSS1 must be at the same potential as VSS.
21 EVSS0 power_in Ground for port; make the same potential as VSS.
22 VDD power_in Positive power supply (1.6 to 5.5 V); must be no less than EVDD0 and EVDD1.
23 EVDD0 power_in Power supply for port (EVDD0 = EVDD1); VDD must be no less than EVDD0.
24 P60/SCLA0 bidirectional Port 6 bit 0 (N-ch open drain, 6 V tolerant) with I2C serial clock SCLA0.
25 P61/SDAA0 bidirectional Port 6 bit 1 (N-ch open drain, 6 V tolerant) with I2C serial data SDAA0.
26 P62/SCLA1 bidirectional Port 6 bit 2 with I2C serial clock SCLA1.
27 P63/SDAA1 bidirectional Port 6 bit 3 with I2C serial data SDAA1.
28 P31/TI03/TO03/INTP4/(PCLBUZ0) bidirectional Port 3 bit 1 with timer input TI03/output TO03, external interrupt INTP4 and PCLBUZ0 (redirectable).
29 P64/TI10/TO10 bidirectional Port 6 bit 4 with timer input TI10 and output TO10.
30 P65/TI11/TO11 bidirectional Port 6 bit 5 with timer input TI11 and output TO11.
31 P66/TI12/TO12 bidirectional Port 6 bit 6 with timer input TI12 and output TO12.
32 P67/TI13/TO13 bidirectional Port 6 bit 7 with timer input TI13 and output TO13.
33 P77/KR7/INTP11/(TxD2) bidirectional Port 7 bit 7 with key return KR7, interrupt INTP11 and TxD2 (redirectable).
34 P76/KR6/INTP10/(RxD2) bidirectional Port 7 bit 6 with key return KR6, interrupt INTP10 and RxD2 (redirectable).
35 P75/KR5/INTP9 bidirectional Port 7 bit 5 with key return KR5 and interrupt INTP9.
36 P74/KR4/INTP8 bidirectional Port 7 bit 4 with key return KR4 and interrupt INTP8.
37 P73/KR3 bidirectional Port 7 bit 3 with key return KR3.
38 P72/KR2/SO21 bidirectional Port 7 bit 2 with key return KR2 and serial data output SO21.
39 P71/KR1/SI21/SDA21 bidirectional Port 7 bit 1 with key return KR1, serial data input SI21 or I/O SDA21.
40 P70/KR0/SCK21/SCL21 bidirectional Port 7 bit 0 with key return KR0, serial clock SCK21 or SCL21.
41 P06 bidirectional Port 0 bit 6 general-purpose I/O.
42 P05 bidirectional Port 0 bit 5 general-purpose I/O.
43 EVSS1 power_in Ground for port; make the same potential as VSS.
44 P80/(SCK10)/(SCL10) bidirectional Port 8 bit 0 with redirectable serial clock SCK10/SCL10.
45 P81/(SI10)/(RxD1)/(SDA10) bidirectional Port 8 bit 1 with redirectable SI10, RxD1 and SDA10.
46 P82/(SO10)/(TxD1) bidirectional Port 8 bit 2 with redirectable SO10 and TxD1.
47 P83 bidirectional Port 8 bit 3 general-purpose I/O.
48 P84/(INTP6) bidirectional Port 8 bit 4 with redirectable interrupt INTP6.
49 P85/(INTP7) bidirectional Port 8 bit 5 with redirectable interrupt INTP7.
50 P86/(INTP8) bidirectional Port 8 bit 6 with redirectable interrupt INTP8.
51 P87/(INTP9) bidirectional Port 8 bit 7 with redirectable interrupt INTP9.
52 P30/INTP3/RTC1HZ/SCK11/SCL11 bidirectional Port 3 bit 0 with interrupt INTP3, RTC 1 Hz output, serial clock SCK11/SCL11.
53 EVDD1 power_in Power supply for port (EVDD0 = EVDD1); VDD must be no less than EVDD1.
54 P50/INTP1/SI11/SDA11 bidirectional Port 5 bit 0 with interrupt INTP1, serial data input SI11 or I/O SDA11.
55 P51/INTP2/SO11 bidirectional Port 5 bit 1 with interrupt INTP2 and serial data output SO11.
56 P52/SO31 bidirectional Port 5 bit 2 with serial data output SO31.
57 P53/SI31/SDA31 bidirectional Port 5 bit 3 with serial data input SI31 or I/O SDA31.
58 P54/SCK31/SCL31 bidirectional Port 5 bit 4 with serial clock SCK31/SCL31.
59 P55/(PCLBUZ1)/(SCK00) bidirectional Port 5 bit 5 with redirectable PCLBUZ1 and SCK00.
60 P56/(INTP1) bidirectional Port 5 bit 6 with redirectable interrupt INTP1.
61 P57/(INTP3) bidirectional Port 5 bit 7 with redirectable interrupt INTP3.
62 P17/TI02/TO02/(SO00)/(TxD0) bidirectional Port 1 bit 7 with timer TI02/TO02, redirectable SO00 and TxD0.
63 P16/TI01/TO01/INTP5/(SI00)/(RxD0) bidirectional Port 1 bit 6 with timer TI01/TO01, interrupt INTP5, redirectable SI00 and RxD0.
64 P15/SCK20/SCL20/(TI02)/(TO02) bidirectional Port 1 bit 5 with serial clock SCK20/SCL20 and redirectable TI02/TO02.
65 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) bidirectional Port 1 bit 4 with RxD2, SI20, SDA20 and redirectable SCLA0, TI03, TO03.
66 P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) bidirectional Port 1 bit 3 with TxD2, SO20 and redirectable SDAA0, TI04, TO04.
67 P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) bidirectional Port 1 bit 2 with SO00, TxD0, TOOLTxD and redirectable INTP5, TI05, TO05.
68 P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) bidirectional Port 1 bit 1 with SI00, RxD0, TOOLRxD, SDA00 and redirectable TI06/TO06.
69 P10/SCK00/SCL00/(TI07)/(TO07) bidirectional Port 1 bit 0 with SCK00/SCL00 and redirectable TI07/TO07.
70 P101 bidirectional Port 10 bit 1 general-purpose I/O.
71 P110/(INTP10) bidirectional Port 11 bit 0 with redirectable interrupt INTP10.
72 P111/(INTP11) bidirectional Port 11 bit 1 with redirectable interrupt INTP11.
73 P146/(INTP4) bidirectional Port 14 bit 6 with redirectable interrupt INTP4.
74 P147/ANI18 bidirectional Port 14 bit 7 with A/D converter analog input ANI18.
75 P100/ANI20 bidirectional Port 10 bit 0 with A/D converter analog input ANI20.
76 P156/ANI14 bidirectional Port 15 bit 6 with analog input ANI14.
77 P155/ANI13 bidirectional Port 15 bit 5 with analog input ANI13.
78 P154/ANI12 bidirectional Port 15 bit 4 with analog input ANI12.
79 P153/ANI11 bidirectional Port 15 bit 3 with analog input ANI11.
80 P152/ANI10 bidirectional Port 15 bit 2 with analog input ANI10.
81 P151/ANI9 bidirectional Port 15 bit 1 with analog input ANI9.
82 P150/ANI8 bidirectional Port 15 bit 0 with analog input ANI8.
83 P27/ANI7 bidirectional Port 2 bit 7 with analog input ANI7.
84 P26/ANI6 bidirectional Port 2 bit 6 with analog input ANI6.
85 P25/ANI5 bidirectional Port 2 bit 5 with analog input ANI5.
86 P24/ANI4 bidirectional Port 2 bit 4 with analog input ANI4.
87 P23/ANI3 bidirectional Port 2 bit 3 with analog input ANI3.
88 P22/ANI2 bidirectional Port 2 bit 2 with analog input ANI2.
89 P21/ANI1/AVREFM bidirectional Port 2 bit 1 with analog input ANI1 or A/D converter reference (- side) AVREFM.
90 P20/ANI0/AVREFP bidirectional Port 2 bit 0 with analog input ANI0 or A/D converter reference (+ side) AVREFP.
91 P130 bidirectional Port 13 bit 0 general-purpose output port.
92 P102/TI06/TO06 bidirectional Port 10 bit 2 with timer input TI06 and output TO06.
93 P04/SCK10/SCL10 bidirectional Port 0 bit 4 with serial clock SCK10/SCL10.
94 P03/ANI16/SI10/RxD1/SDA10 bidirectional Port 0 bit 3 with analog input ANI16, SI10, RxD1 and SDA10.
95 P02/ANI17/SO10/TxD1 bidirectional Port 0 bit 2 with analog input ANI17, SO10 and TxD1.
96 P01/TO00 bidirectional Port 0 bit 1 with timer output TO00.
97 P00/TI00 bidirectional Port 0 bit 0 with timer input TI00.
98 P145/TI07/TO07 bidirectional Port 14 bit 5 with timer input TI07 and output TO07.
99 P144/SO30/TxD3 bidirectional Port 14 bit 4 with serial data output SO30 and TxD3.
100 P143/SI30/RxD3/SDA30 bidirectional Port 14 bit 3 with SI30, RxD3 and SDA30.

Key specifications

Parameter Value
Manufacturer RENESAS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 6.5 V 51
EVDD0, EVDD1 supply voltage EVDD0, EVDD1 -0.5 6.5 V EVDD0 = EVDD1 51
EVSS0, EVSS1 voltage EVSS0, EVSS1 -0.5 0.3 V EVSS0 = EVSS1 51
REGC pin input voltage VIREGC -0.3 2.8 V REGC pin; alt. -0.3 to VDD +0.3 (Note 1) 51
Input voltage (port pins P00-P07 etc.) VI1 -0.3 V Max EVDD0 +0.3 and VDD +0.3 (Note 2) 51
Input voltage (N-ch open-drain P60-P63) VI2 -0.3 6.5 V P60-P63 (N-ch open-drain) 51
Input voltage (P20-P27, P121-P124, P137, P150-P156, EXCLK, EXCLKS, RESET) VI3 -0.3 V Max VDD +0.3 (Note 2) 51
Output voltage (port pins) VO1 -0.3 V Max EVDD0 +0.3 and VDD +0.3 (Note 2) 51
Output voltage (P20-P27, P150-P156) VO2 -0.3 V Max VDD +0.3 (Note 2) 51
Analog input voltage ANI16-ANI26 VAI1 -0.3 V Max EVDD0 +0.3 and AVREF(+) +0.3 (Notes 2, 3) 51
Analog input voltage ANI0-ANI14 VAI2 -0.3 V Max VDD +0.3 and AVREF(+) +0.3 (Notes 2, 3) 51
Output current, high per pin IOH1 -40 mA Per pin 52
Output current, high total all pins IOH1 -170 mA Total of all pins 52
Output current, high per pin (P20-P27, P150-P156) IOH2 -0.5 mA Per pin, P20-P27, P150-P156 52
Output current, high total (P20-P27, P150-P156) IOH2 -2 mA Total of all pins 52
Output current, low per pin IOL1 40 mA Per pin 52
Output current, low total all pins IOL1 170 mA Total of all pins 52
Output current, low per pin (P20-P27, P150-P156) IOL2 1 mA Per pin, P20-P27, P150-P156 52
Output current, low total (P20-P27, P150-P156) IOL2 5 mA Total of all pins 52
Operating ambient temperature TA -40 85 °C In normal operation mode 52
Storage temperature Tstg -65 150 °C 52
X1 clock oscillation frequency fX 1 20 MHz 2.7 V ≤ VDD ≤ 5.5 V 53
X1 clock oscillation frequency fX 1 16 MHz 2.4 V ≤ VDD < 2.7 V 53
X1 clock oscillation frequency fX 1 8 MHz 1.8 V ≤ VDD < 2.4 V 53
X1 clock oscillation frequency fX 1 4 MHz 1.6 V ≤ VDD < 1.8 V 53
XT1 clock oscillation frequency fX 32 32.768 35 kHz Crystal resonator 53
High-speed on-chip oscillator clock frequency (selectable range) fIH 1 32 MHz Selectable frequency range 53
High-speed on-chip oscillator clock frequency accuracy fIH -1 1 % -20 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V 53
High-speed on-chip oscillator clock frequency accuracy fIH -5 5 % -20 to +85°C, 1.6 V ≤ VDD < 1.8 V 53
Low-speed on-chip oscillator clock frequency accuracy fIL -15 15 % 53
Input voltage, high (TTL input buffer) VIH2 2.2 V TTL input buffer, 4.0 V ≤ EVDD0 ≤ 5.5 V (max EVDD0) 56
Input voltage, high (TTL input buffer) VIH2 2 V TTL input buffer, 3.3 V ≤ EVDD0 < 4.0 V (max EVDD0) 56
Input voltage, high (TTL input buffer) VIH2 1.5 V TTL input buffer, 1.6 V ≤ EVDD0 < 3.3 V (max EVDD0) 56
Input voltage, high (P60-P63) VIH4 6 V P60-P63; min 0.7EVDD0 56
Input voltage, low (normal input buffer) VIL1 0 V Normal input buffer; max 0.2EVDD0 56
Input voltage, low (P60-P63) VIL4 0 V P60-P63; max 0.3EVDD0 56
Input voltage, low (TTL input buffer) VIL2 0 0.8 V TTL input buffer, 4.0 V ≤ EVDD0 ≤ 5.5 V 56
Input voltage, low (TTL input buffer) VIL2 0 0.5 V TTL input buffer, 3.3 V ≤ EVDD0 < 4.0 V 56
Input voltage, low (TTL input buffer) VIL2 0 0.32 V TTL input buffer, 1.6 V ≤ EVDD0 < 3.3 V 56
Output voltage, low VOL1 1.3 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 20 mA 57
Output voltage, low VOL1 0.7 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 8.5 mA 57
Output voltage, low VOL1 0.6 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 3.0 mA 57
Output voltage, low VOL1 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 57
Output voltage, low (P20-P27, P150-P156) VOL2 0.4 V 1.6 V ≤ VDD ≤ 5.5 V, IOL2 = 400 µA 57
Output voltage, low (P60-P63) VOL3 2 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 15.0 mA 57
Output voltage, low (P60-P63) VOL3 0.4 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 5.0 mA 57
Input leakage current, high (port pins) ILIH1 1 µA VI = EVDD0 58
Input leakage current, low (port pins) ILIL1 -1 µA VI = EVSS0 58
Input leakage current, high (P20-P27, P137, P150-P156, RESET) ILIH2 1 µA VI = VDD 58
Input leakage current, low (P20-P27, P137, P150-P156, RESET) ILIL2 -1 µA VI = VSS 58
Input leakage current, high (P121-P124, X1, X2, XT1, XT2, EXCLK, EXCLKS) ILIH3 1 µA VI = VDD, in input port or external clock input 58
Input leakage current, low (P121-P124, X1, X2, XT1, XT2, EXCLK, EXCLKS) ILIL3 -1 µA VI = VSS, in input port or external clock input 58
On-chip pull-up resistance RU 10 20 100 kΩ VI = EVSS0, in input port 58
Data retention supply voltage VDDDR 1.46 5.5 V 117
POR detection voltage (rising) VPOR 1.47 1.51 1.55 V The power supply voltage is rising 114
POR detection voltage (falling) VPDR 1.46 1.5 1.54 V The power supply voltage is falling 114

CAD (KiCad official)

  • Symbol: R5F100PLAFB#10
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: r5f100plafb-10-etched.step / r5f100plafb-10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); r5f100plafb-10.step / r5f100plafb-10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (219 pp, sha256 363a7745eaa9e002, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF