component
QCPL-074H-500E
Public Made by Adomby adom
Broadcom AVAGO Transistor, Photovoltaic Output Optoisolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownQCPL-074H-500E
Broadcom AVAGO · Transistor, Photovoltaic Output Optoisolators · SOP-8
QCPL-074H-500E from Broadcom AVAGO, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ANODE1 | input | LED anode for channel 1; a series limiting resistor of 80 ohm at 3.3 V or 210 ohm at 5 V is recommended, with input ON current 9 to 18 mA. |
| 2 | CATHODE1 | passive | LED cathode for channel 1 of the dual-channel optocoupler. |
| 3 | CATHODE2 | passive | LED cathode for channel 2 of the dual-channel optocoupler. |
| 4 | ANODE2 | input | LED anode for channel 2; a series limiting resistor of 80 ohm at 3.3 V or 210 ohm at 5 V is recommended, with input ON current 9 to 18 mA. |
| 5 | GND | power_in | Ground reference for the output stages and the detector ICs; a 0.1 uF bypass capacitor must be connected between pins 5 and 8. |
| 6 | VO2 | output | CMOS logic output of channel 2 (logic high when the LED is off, logic low when on), with 0.01 uF to 0.1 uF bypass recommended across VDD and GND. |
| 7 | VO1 | output | CMOS logic output of channel 1 (logic high when the LED is off, logic low when on). |
| 8 | VDD | power_in | Supply voltage: 4.5 V to 5.5 V or 3.0 V to 3.6 V, with a minimum of 3.0 V required before powering up the output-connected component. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SOP-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Forward Voltage | VF | 1.3 | 1.5 | 1.8 | V | IF = 14mA | 5 |
| Input Reverse Breakdown Voltage | BVR | 5 | V | IR = 10 µA | 5 | ||
| Logic Low Output Voltage (3.3V) | VOL | 0.35 | 0.8 | V | IF = 14mA, IO = 4mA, VDD=3.3V | 5 | |
| Logic Low Output Voltage (5V) | VOL | 0.2 | 0.8 | V | IF = 14mA, IO = 4mA, VDD=5V | 5 | |
| Input Threshold Current | ITH | 4.5 | 8.8 | mA | IOL = 20 µA | 5 | |
| Logic Low Output Supply Current (QCPL-074H) | IDDL | 8.3 | 12 | mA | IF = 14 mA | 5 | |
| Logic High Output Supply Current (QCPL-074H) | IDDH | 7.6 | 12 | mA | IF = 0 | 5 | |
| Propagation Delay Time to Logic Low Output (3.3V) | tPHL | 29 | 40 | ns | IF = 14mA, CL = 15pF, VDD=3.3V, CMOS Signal Levels | 6 | |
| Propagation Delay Time to Logic Low Output (5V) | tPHL | 50 | ns | IF = 14mA, CL = 15pF, VDD=5V, CMOS Signal Levels | 6 | ||
| Propagation Delay Time to Logic High Output (3.3V) | tPLH | 22 | 40 | ns | IF = 14mA, CL = 15pF, VDD=3.3V, CMOS Signal Levels | 6 | |
| Propagation Delay Time to Logic High Output (5V) | tPLH | 50 | ns | IF = 14mA, CL = 15pF, VDD=5V, CMOS Signal Levels | 6 | ||
| Pulse Width | tPW | 66.7 | ns | 6 | |||
| Pulse Width Distortion (3.3V) | /PWD/ | 0 | 7 | 25 | ns | IF = 14mA, CL = 15pF, VDD=3.3V, CMOS Signal Levels | 6 |
| Pulse Width Distortion (5V) | /PWD/ | 30 | ns | IF = 14mA, CL = 15pF, VDD=5V, CMOS Signal Levels | 6 | ||
| Propagation Delay Skew | tPSK | 30 | ns | IF = 14mA, CL = 15pF, CMOS Signal Levels | 6 | ||
| Output Rise Time (10%-90%) | tR | 20 | ns | IF = 14mA, CL = 15pF, CMOS Signal Levels | 6 | ||
| Output Fall Time (90%-10%) | tF | 25 | ns | IF = 14mA, CL = 15pF, CMOS Signal Levels | 6 | ||
| Common Mode Transient Immunity at Logic High Output | /CMH/ | 10 | 15 | kV/µs | VCM = 1000 V, TA = 25°C, IF = 0 mA | 6 | |
| Common Mode Transient Immunity at Logic Low Output | /CML/ | 10 | 15 | kV/µs | VCM = 1000 V, TA = 25°C, IF = 14 mA | 6 | |
| Input-Output Insulation Leakage Current | II-O | 1 | µA | 45% RH, t = 5 s, VI-O = 3 kV DC, TA = 25°C | 6 | ||
| Input-Output Momentary Withstand Voltage | VISO | 3750 | Vrms | RH ≤ 50%, t = 1 min., TA = 25°C | 6 | ||
| Input-Output Capacitance | CI-O | 0.6 | pF | f = 1 MHz, TA = 25°C | 6 | ||
| Storage Temperature | TS | -55 | 125 | °C | 5 | ||
| Ambient Operating Temperature | TA | -40 | 105 | °C | 5 | ||
| Supply Voltage | VDD | 0 | 6 | V | 5 | ||
| Output Voltage | VO | -0.5 | V | Upper limit printed as VDD + 0.5 V; not numeric | 5 | ||
| Average Forward Input Current | IF | 20 | mA | 5 | |||
| Average Output Current | IO | 10 | mA | 5 | |||
| Lead Solder Temperature | 260 | °C | 10 sec., 1.6 mm below seating plane | 5 | |||
| Ambient Operating Temperature | TA | -40 | 105 | °C | 5 | ||
| Supply Voltage (5V range) | VDD | 4.5 | 5.5 | V | 5V operation | 5 | |
| Supply Voltage (3.3V range) | VDD | 3 | 3.6 | V | 3.3V operation | 5 | |
| Input Current (ON) | IF | 9 | 18 | mA | 5 | ||
| Supply Voltage Slew Rate | SR | 0.5 | 500 | V/ms | 5 |
CAD (KiCad official)
- Symbol:
QCPL-074H-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
qcpl-074h-500e-etched.step/qcpl-074h-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);qcpl-074h-500e.step/qcpl-074h-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (10 pp, sha256
87574500a3d7b62a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).