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PY32MD310K18U7TR
Public Made by Adomby adom
PUYA Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPY32MD310K18U7TR
PUYA · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)
PY32MD310K18U7TR from PUYA, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INN1 | input | Negative input of the channel 1 low-offset op-amp. |
| 2 | INP1 | input | Positive input of the channel 1 low-offset op-amp. |
| 3 | INN2 | input | Negative input of the channel 2 low-offset op-amp. |
| 4 | INP2 | input | Positive input of the channel 2 low-offset op-amp. |
| 5 | LDO | power_out | 5 V LDO output; connect an external 1 µF capacitor to ground. |
| 6 | VIN | power_in | Input supply for the gate driver; connect an external 1 µF capacitor to ground. |
| 7 | PGND | power_in | Power ground for the gate driver, connected to the gate driver stage. |
| 8 | LO1 | bidirectional | Port PA10 (COM: normal 5 V port with analog I/O capability), also the channel 1 low-side gate driver output LO1. |
| 9 | HO1 | bidirectional | Port PB1 (COM), also the channel 1 high-side gate driver output HO1. |
| 10 | LO2 | bidirectional | Port PA8 (COM), also the channel 2 low-side gate driver output LO2. |
| 11 | HO2 | bidirectional | Port PA7 (COM), also the channel 2 high-side gate driver output HO2. |
| 12 | LO3 | bidirectional | Port PB3 (COM), also the channel 3 low-side gate driver output LO3. |
| 13 | HO3 | bidirectional | Port PA1 (COM), also the channel 3 high-side gate driver output HO3. |
| 14 | PB4 | bidirectional | General-purpose I/O (COM, analog I/O capable); alternate functions include SPI1_MISO, TIM3_CH1, USART1_CTS and TIM17_BKIN. |
| 15 | PB5 | bidirectional | General-purpose I/O (COM, analog I/O capable); alternate functions include SPI1_MOSI, TIM3_CH2, LPTIM_IN1 and COMP1_OUT. |
| 16 | PB7 | bidirectional | General-purpose I/O (COM, analog I/O capable); alternate functions include USART1_RX, COMP2_INM, PVD_IN and I2C_SDA. |
| 17 | PA14-SWCLK | bidirectional | SWD clock (SWCLK); after reset this pin is SWCLK with an internal pull-down enabled. |
| 18 | PA13-SWDIO | bidirectional | SWD data I/O (SWDIO); after reset this pin is SWDIO with an internal pull-up enabled. |
| 19 | PB8 | bidirectional | General-purpose I/O (COM, analog I/O capable); alternate functions include COMP1_INP, TIM16_CH1, I2C1_SCL and USART2_TX. |
| 20 | VCC | power_in | Main power supply, 1.7 V to 5.5 V; supplies the analog modules and I/O ring. |
| 21 | PF0-OSC_IN | bidirectional | Port PF0 (COM, analog I/O capable); also the HSE oscillator input OSC_IN. |
| 22 | PF1-OSC_OUT | bidirectional | Port PF1 (COM, analog I/O capable); also the HSE oscillator output OSC_OUT. |
| 23 | PF2-NRST | bidirectional | Reset port (RST: internal weak pull-up, no analog I/O); function is PF2 or NRST, selected through option bytes. |
| 24 | PF3 | bidirectional | General-purpose I/O (COM, analog I/O capable); alternate functions include COMP2_INP, USART1_TX and RTC_OUT. |
| 25 | PA0 | bidirectional | General-purpose I/O (COM, analog I/O capable); alternate functions include ADC_IN0, COMP1_INM and COMP1_OUT. |
| 26 | PA2 | bidirectional | General-purpose I/O; alternate functions include SPI1_MOSI, USART1_TX, USART2_TX and COMP2_OUT. |
| 27 | PA3 | bidirectional | General-purpose I/O; alternate functions include SPI2_MISO, USART1_RX, USART2_RX and I2C_SCL. |
| 28 | PA4 | bidirectional | General-purpose I/O; alternate functions include SPI1_NSS, USART1_CK, SPI2_MOSI and TIM14_CH1. |
| 29 | PA5 | bidirectional | General-purpose I/O; alternate functions include SPI1_SCK, LPTIM1_ETR, USART2_RX and TIM3_CH2. |
| 30 | PA6 | bidirectional | General-purpose I/O; alternate functions include SPI1_MISO, TIM3_CH1, TIM1_BKIN and COMP1_OUT. |
| 31 | AO2 | output | Output of the channel 2 low-offset op-amp. |
| 32 | AO1 | output | Output of the channel 1 low-offset op-amp. |
| 33 | VSS | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PUYA |
| Package | QFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage VCC | VCC | -0.3 | 6.25 | V | 29 | ||
| Input voltage on other pins | VIN | -0.3 | V | 29 | |||
| Total current into VCC pin (supply current) | IVCC | 100 | mA | 29 | |||
| Total current out of VSS pin (sink current) | IVSS | 100 | mA | 29 | |||
| Output sink current per COM IO pin | IIO(PIN) | 20 | mA | 29 | |||
| Sum of output source current, all IO pins | -20 | mA | 29 | ||||
| Storage temperature range | TSTG | -65 | 150 | ℃ | 30 | ||
| Operating temperature range | TO | -40 | 105 | ℃ | 30 | ||
| Internal AHB clock frequency | fHCLK | 0 | 48 | MHz | 30 | ||
| Internal APB clock frequency | fPCLK | 0 | 48 | MHz | 30 | ||
| Standard operating voltage | VCC | 1.7 | 5.5 | V | 30 | ||
| IO input voltage | VIN | -0.3 | V | 30 | |||
| Ambient temperature | TA | -40 | 105 | ℃ | 30 | ||
| Junction temperature | TJ | -40 | 125 | ℃ | 30 | ||
| VCC rise rate | tVCC | 0 | us/V | 30 | |||
| VCC fall rate | tVCC | 20 | us/V | 30 | |||
| Reset timeout | tRSTTEMPO | 4 | 7.5 | ms | 30 | ||
| POR/PDR reset threshold, rising edge | VPOR/PDR | 1.5 | 1.6 | 1.7 | V | 上升沿 (rising edge) | 30 |
| POR/PDR reset threshold, falling edge | VPOR/PDR | 1.45 | 1.55 | 1.65 | V | 下降沿 (falling edge) | 30 |
| BOR threshold 1, rising edge | VBOR1 | 1.7 | 1.8 | 1.9 | V | 上升沿 (rising edge) | 30 |
| BOR threshold 1, falling edge | VBOR1 | 1.6 | 1.7 | 1.8 | V | 下降沿 (falling edge) | 30 |
| BOR threshold 2, rising edge | VBOR2 | 1.9 | 2 | 2.1 | V | 上升沿 (rising edge) | 30 |
| Temperature sensor VTS linearity with temperature | TL | 2 | ℃ | 39 | |||
| Temperature sensor average slope | Avg_Slope | 2.3 | 2.5 | 2.7 | mV/℃ | 39 | |
| Temperature sensor voltage at 30℃(±5℃) | V30 | 0.742 | 0.76 | 0.785 | V | 39 | |
| Temperature sensor start-up time entering continuous mode | tSTART | 70 | 120 | us | 39 | ||
| ADC sampling time when reading temperature | tS_temp | 9 | us | 39 | |||
| Internal reference voltage | VREFINT | 1.17 | 1.2 | 1.23 | V | 39 | |
| Internal reference voltage start time | Tstart_vrefint | 10 | 15 | us | 40 | ||
| Internal reference voltage temperature coefficient | Tcoeff | 100 | ppm/℃ | 40 | |||
| Current consumption from VCC (internal reference) | Ivcc | 12 | 20 | μA | 40 | ||
| Gate driver absolute maximum supply voltage range | VIN | -0.3 | 45 | V | 44 | ||
| Gate driver recommended supply voltage range | VIN | 6 | 36 | V | 44 | ||
| Gate driver LDO output voltage range (recommended) | VLDO | 4.5 | 5.5 | V | 44 | ||
| Low-side gate driver output voltage (recommended) | VLO1,2,3 | 0 | 12 | V | 44 | ||
| Gate driver supply voltage range | VIN | 6 | 36 | V | 44 | ||
| LDO output voltage | VLDO | 4.75 | 5 | 5.25 | V | IOUT=1mA,VIN=12V | 44 |
| VGS clamp voltage driving external PMOS | VPCLAMP | -12 | -10 | -9 | V | 驱动外部 PMOS | 45 |
| VGS clamp voltage driving external NMOS | VNCLAMP | 9 | 10 | 12 | V | 驱动外部 NMOS | 45 |
| Dead time | tDT | 300 | 500 | 800 | nS | 45 | |
| Timer resolution time | tres(TIM) | 1 | tTIMxCLK | 40 | |||
| Timer resolution time | tres(TIM) | 20.833 | ns | fTIMxCLK = 48 MHz | 40 | ||
| Timer external clock frequency on CH1 to CH4 | fEXT | 24 | MHz | fTIMxCLK = 48 MHz | 40 | ||
| 16-bit counter clock period | tCOUNTER | 1 | 65536 | tTIMxCLK | 40 | ||
| 16-bit counter clock period | tCOUNTER | 0.020833 | 1365 | us | fTIMxCLK = 48 MHz | 40 | |
| IWDG overflow time, prescaler /4 | 0.122 | 499.712 | ms | 时钟选择 LSI; PR[2:0]=0 | 40 | ||
| IWDG overflow time, prescaler /8 | 0.244 | 999.424 | ms | 时钟选择 LSI; PR[2:0]=1 | 40 | ||
| IWDG overflow time, prescaler /16 | 0.488 | 1998.85 | ms | 时钟选择 LSI; PR[2:0]=2 | 40 | ||
| IWDG overflow time, prescaler /32 | 0.976 | 3997.7 | ms | 时钟选择 LSI; PR[2:0]=3 | 40 | ||
| IWDG overflow time, prescaler /64 | 1.952 | 7995.39 | ms | 时钟选择 LSI; PR[2:0]=4 | 40 | ||
| IWDG overflow time, prescaler /128 | 3.904 | 15990.8 | ms | 时钟选择 LSI; PR[2:0]=5 | 40 | ||
| IWDG overflow time, prescaler /256 | 7.808 | 31981.6 | ms | 时钟选择 LSI; PR[2:0]=6 or 7 | 40 | ||
| WWDG overflow time, prescaler 1*4096 | 0.085 | 5.461 | ms | 时钟选择 48MHz PCLK; WDGTB[1:0]=0 | 41 | ||
| WWDG overflow time, prescaler 2*4096 | 0.171 | 10.923 | ms | 时钟选择 48MHz PCLK; WDGTB[1:0]=1 | 41 | ||
| WWDG overflow time, prescaler 4*4096 | 0.341 | 21.845 | ms | 时钟选择 48MHz PCLK; WDGTB[1:0]=2 | 41 | ||
| WWDG overflow time, prescaler 8*4096 | 0.683 | 43.691 | ms | 时钟选择 48MHz PCLK; WDGTB[1:0]=3 | 41 | ||
| Minimum I2C CLK frequency | fI2CCLK(min) | 2 | MHz | Standard-mode | 41 | ||
| Minimum I2C CLK frequency | fI2CCLK(min) | 9 | MHz | Fast-mode | 41 | ||
| Limiting duration of I2C filter-suppressed spikes | tAF | 50 | 260 | ns | 41 |
CAD (KiCad official)
- Symbol:
PY32MD310K18U7TR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
py32md310k18u7tr-etched.step/py32md310k18u7tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);py32md310k18u7tr.step/py32md310k18u7tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PUYA datasheet (48 pp, sha256
a1419850cd1069c6, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).