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PY32F002BF15U6TR

PUYA · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(3x3)

PY32F002BF15U6TR from PUYA, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC0-NRST	bidirectional	Reset-type I/O (RST structure) with internal weak pull-up and no analog I/O capability, shared with the NRST reset and SWDIO functions, plus TIM1_CH1N, ADC_IN5 and EVENTOUT.
2	PC1-OSCIN	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_MISO and OSCIN functions.
3	PB7-OSCOUT	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_MOSI, OSCOUT and TIM14_CH1 functions.
4	VSS	power_in	Ground pin; the datasheet states all voltages are referenced to VSS.
5	PB6(SWDIO)	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_MISO, ADC_IN6, USART_TX, I2C_SDA and SWDIO functions.
6	VCC	power_in	Digital power supply pin; operating range 1.7 V to 5.5 V, with absolute maximum VCC of -0.3 V to 6.25 V.
7	PB5	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_NSS, USART_RX, TIM1_CH3 and TIM14_CH1 functions.
8	PB4	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_TX, I2C_SDA and TIM1_BKIN functions.
9	PB3	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_CK, I2C_SCL, TIM1_ETR and CMP1_OUT functions.
10	PB2	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_SCK, USART_CTS, TIM1_CH1N and TIM1_CH3 functions.
11	PB1	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_RTS, ADC_IN0, TIM1_CH2N, CMP1_INP, TIM1_CH4, CMP1_INM and MCO functions.
12	PB0	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_SCK, ADC_IN7, USART_CK, CMP1_INM, TIM1_CH2 and TIM1_CH3N functions.
13	PA0	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_MOSI and TIM1_CH1 functions.
14	PA1	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_MISO and TIM1_CH2 functions.
15	PA2(SWCLK)	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_RX, I2C_SCL, SWCLK, TIM1_CH4 and CMP2_OUT functions.
16	PA3	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_TX, ADC_IN1, CMP2_INP, TIM1_CH2 and CMP2_INM functions.
17	PA4	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_RX, ADC_IN2, TIM1_CH3, CMP2_INM and TIM14_CH1 functions.
18	PA5	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with USART_CK, TIM1_CH1 and TIM14_CH1 functions.
19	PA6	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_NSS, ADC_IN3, USART_TX, External_clock_in and EVENTOUT functions.
20	PA7	bidirectional	General-purpose I/O in COM structure (normal 5 V port with analog I/O support), also listed with SPI_MOSI, ADC_IN4, USART_TX, USART_RX, TIM1_CH4 and MCO functions.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	PUYA
Package	QFN-20-EP(3x3)
Category	Embedded Processors & Controllers
Pins	21

CAD (KiCad official)

Symbol: PY32F002BF15U6TR
Footprint: Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
3D model files: py32f002bf15u6tr-etched.step / py32f002bf15u6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); py32f002bf15u6tr.step / py32f002bf15u6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: PUYA datasheet (50 pp, sha256 fbb3d3b7645a5643, retrieved 2026-10-09, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF