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PY25Q128HA-SUH-IT

Public Made by Adom

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PUYA） NOR FLASH, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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PY25Q128HA-SUH-IT

PUYA） · NOR FLASH · SOP-8

PY25Q128HA-SUH-IT from PUYA）, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip select input for the device (active low, per the ordering and interface description; the datasheet lists it as 'Chip select').
2 SO bidirectional Serial data output for 1 x I/O; also serves as SIO1, a serial data input and output for the 4 x I/O read mode.
3 WP# bidirectional Write protection, active low; also serves as SIO2 for the 4 x I/O read mode, and the WP# function is only available for Standard/Dual SPI.
4 GND power_in Ground of the device.
5 SI bidirectional Serial data input for 1 x I/O; also serves as SIO0, a serial data input and output for the 4 x I/O read mode.
6 SCLK input Serial interface clock input.
7 HOLD#/RESET# bidirectional Pauses the device without deselecting it (HOLD#) or acts as hardware reset (RESET#, active low, minimum 1 us) depending on the HOLD/RST configure bit; also serves as SIO3 for the 4 x I/O read mode.
8 VCC power_in Power supply of the device, specified from 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer PUYA）
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 8
Maximum Operation Voltage 4 V 8
Voltage on Any Pin with respect to Ground -0.6 V 8
DC Output Current 5 mA 8
Output Capacitance COUT 8 pF VOUT=GND 8
Input Capacitance CIN 6 pF VIN=GND 8
Supply voltage VCC 2.7 3.6 V 9
Ambient operating temperature (Grade I) Ta -40 85 °C Grade I 9
Deep power down current IDPD 1 5 uA CS#=Vcc, all other inputs at 0V or Vcc 9
Standby current ISB 15 30 uA CS#, HOLD#, WP#=VIH all inputs at CMOS levels 9
Read current (STR) (1 IO) 3 6 mA f=50MHz; IOUT=0mA 9
Read current (STR) (1 IO) 4 9 mA f=85MHz; IOUT=0mA 9
Read current (STR) (1 IO) 5.5 13 mA f=133MHz; IOUT=0mA 9
Read current (STR) (2,4 IO) ICC1 5 10 mA f=50MHz; IOUT=0mA 9
Read current (STR) (2,4 IO) ICC1 7 13 mA f=85MHz; IOUT=0mA 9
Read current (STR) (2,4 IO) ICC1 10.5 18 mA f=133MHz; IOUT=0mA 9
Read current (DTR) (1, 2, 4 IO) ICC2 9 15 mA f=66MHz; IOUT=0mA 9
Program current ICC3 6 9 mA CS#=Vcc 9
Erase current ICC4 8 12 mA CS#=Vcc 9
Input load current ILI 1 uA All inputs at CMOS level 9
Output leakage ILO 1 uA All inputs at CMOS level 9
Input low voltage VIL -0.5 V 9
Output low voltage VOL 0.2 V IOL=100uA 9
Clock Frequency for all instructions except for special marking fSCLK 133 MHz 10
Clock Frequency for READ instructions fRSCLK 80 MHz 10
Clock Frequency for 4IO WORD READ instructions fWSCLK 104 MHz 10
Clock Frequency for DTR instructions fDSCLK 80 MHz 10
Clock High Time tCH 3.3 ns 10
Clock Low Time, 45% x (1/fSCLK) tCL 3.3 ns 10
CS# Active Setup Time (relative to SCLK) tSLCH 5 ns 10
CS# Not Active Hold Time (relative to SCLK) tCHSL 5 ns 10
Data in Setup Time tDVCH 2 ns 10
Data in Hold Time tCHDX 3 ns 10
CS# Active Hold Time (relative to SCLK) tCHSH 5 ns 10
CS# Not Active Setup Time (relative to SCLK) tSHCH 5 ns 10
CS# Deselect Time from Read to next Read 20 ns 10
CS# Deselect Time from Write, Erase, Program to Read Status Register tSHSL 30 ns 10
Output Disable Time tSHQZ 6 ns 10
Clock Low to Output Valid tCLQV 7 ns Loading 30pF 10
Clock Low to Output Valid tCLQV 6 ns Loading 15pF 10
Output Hold Time tCLQX 1 ns 10
HOLD# to Output Low-Z tHHQX 6 ns 10
HOLD# to Output High-Z tHLQZ 6 ns 10
Write Protect Setup Time tWHSL 20 ns 10
Write Protect Hold Time tSHWL 100 ns 10
CS# High to Deep Power-down Mode tDP 3 us 10
CS# High to Standby Mode Without Electronic Signature Read tRES1 20 us 10
Write Status Register Cycle Time tW 8 12 ms 10
Erase Suspend Latency TESL 30 us 13
Program Suspend Latency TPSL 30 us 13
Latency between Program Resume and next Suspend TPRS 0.3 us 13
Latency between Erase Resume and next Suspend TERS 0.3 us 13
Program Security Registers time (up to 256 bytes) tPSR 0.5 2.4 ms 13
Erase Security Registers time tESR 50 240 ms 13
Page program time (up to 256 bytes) tPP 0.5 2.4 ms 13
Sector erase time tSE 50 240 ms 13
Block erase time for 32K bytes tBE1 0.16 0.8 s 13
Block erase time for 64K bytes tBE2 0.3 1.2 s 13
Chip erase time tCE 50 120 s 13

CAD (KiCad official)

  • Symbol: PY25Q128HA-SUH-IT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: py25q128ha-suh-it-etched.step / py25q128ha-suh-it-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); py25q128ha-suh-it.step / py25q128ha-suh-it.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA） datasheet (109 pp, sha256 7c517dc149feb529, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF