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PXE1610CDN-G003
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Infineon Technologies DC-DC Converters, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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PXE1610CDN-G003
Infineon Technologies · DC-DC Converters · VQFN-48-EP(6x6)
PXE1610CDN-G003 from Infineon Technologies, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BPWM1 | output | Loop_B phase #1 PWM output (3.3V CMOS) that drives the PWM input of a power stage/FET driver IC, as described for APWM1. |
| 2 | APWM6 | output | Loop_A phase #6 PWM output (3.3V CMOS) that drives the PWM input of a power stage/FET driver IC; leave unused PWM pins unconnected (floating). |
| 3 | APWM5 | output | Loop_A phase #5 PWM output (3.3V CMOS) that drives the PWM input of a power stage/FET driver IC; leave unused PWM pins unconnected (floating). |
| 4 | APWM4 | output | Loop_A phase #4 PWM output (3.3V CMOS) that drives the PWM input of a power stage/FET driver IC; leave unused PWM pins unconnected (floating). |
| 5 | APWM3 | output | Loop_A phase #3 PWM output (3.3V CMOS) that drives the PWM input of a power stage/FET driver IC; leave unused PWM pins unconnected (floating). |
| 6 | APWM2 | output | Loop_A phase #2 PWM output (3.3V CMOS) that drives the PWM input of a power stage/FET driver IC; leave unused PWM pins unconnected (floating). |
| 7 | APWM1 | output | Loop_A phase #1 PWM output (3.3V CMOS) used to drive the PWM input of the power stage/FET driver IC; unused PWM pins should be left unconnected (floating). |
| 8 | SDA | bidirectional | SMBus/I2C bidirectional serial data signal, open-drain. |
| 9 | SCL | bidirectional | SMBus/I2C bidirectional serial clock signal, open-drain. |
| 10 | RESET# | input | Input (3.3V CMOS) that puts the controller into its lowest power dissipation mode; may be left floating, but a 1kΩ pull-up to 3.3V is recommended if routed to a board trace. |
| 11 | AVRRDY | output | Open-drain voltage regulator ready output, asserted when the controller is ready to accept SVID commands after AVREN is asserted and pulled low on a shutdown fault; requires an external pull-up (1kΩ recommended). |
| 12 | AVREN | input | Active-high output enable input (1.2V CMOS) that activates the digital controller subject to power-on-reset and fault status; it must not be left open because there is no internal bias. |
| 13 | VRHOT# | output | Open-drain active-low external temperature indicator, asserted at the temperature defined by the programmable TEMP_MAX register. |
| 14 | PINALRT# | output | Open-drain active-low input supply power alert, asserted when input power reaches the threshold set by the PIN_MAX register; may be left open if unused. |
| 15 | MP0 | bidirectional | Multi-purpose pin configurable as BVRRDY, FAULT1, FAULT2, ADREN, BDREN, or LPM, and programmable as 3.3V CMOS, open drain, or analog; unused MP pins may be left open. |
| 16 | MP1 | bidirectional | Multi-purpose pin configurable as BVREN, BVRRDY, FAULT1, FAULT2, ADREN, BDREN, or SMBAlert#, and programmable as 3.3V CMOS, open drain, or analog. |
| 17 | VCLK | input | SVID clock interface input (1.2V CMOS); if the SVID interface is not used, tie VCLK, VDIO and VALRT# together and pull up to VD12 through 1kΩ. |
| 18 | VDIO | bidirectional | SVID bidirectional open-drain data interface; if SVID is not used, tie it together with VCLK and VALRT# and pull up to VD12 through 1kΩ. |
| 19 | VALRT# | output | Open-drain active-low SVID ALERT# output asserted to indicate the VR status has changed; if SVID is not used, tie it together with VCLK and VDIO and pull up to VD12 through 1kΩ. |
| 20 | MP2 | bidirectional | Multi-purpose pin configurable as FAULT2, SMBAlert#, or IMON, and programmable as 3.3V CMOS, open drain, or analog. |
| 21 | AVSEN | input | Loop_A positive voltage sense input to the precision differential remote sense amplifier, to be connected to the remote load sense pin; an RC filter (10Ω and 220pF) is recommended close to the controller. |
| 22 | AVREF | input | Loop_A negative voltage sense input paired with AVSEN for the precision differential remote sense amplifier. |
| 23 | AIREF1 | input | Loop_A phase #1 current sense negative input, paired with AISEN1 for differential channel current sensing; unused pairs may be left open or tied to ground. |
| 24 | AISEN1 | input | Loop_A phase #1 current sense positive input, paired with AIREF1, used for channel current balancing, loadline regulation and overcurrent protection. |
| 25 | AIREF2 | input | Loop_A phase #2 current sense negative input, paired with AISEN2; unused pairs may be left open or tied to ground. |
| 26 | AISEN2 | input | Loop_A phase #2 current sense positive input, paired with AIREF2, used for channel current balancing, loadline regulation and overcurrent protection. |
| 27 | AIREF3 | input | Loop_A phase #3 current sense negative input, paired with AISEN3; unused pairs may be left open or tied to ground. |
| 28 | AISEN3 | input | Loop_A phase #3 current sense positive input, paired with AIREF3, used for channel current balancing, loadline regulation and overcurrent protection. |
| 29 | AIREF4 | input | Loop_A phase #4 current sense negative input, paired with AISEN4; unused pairs may be left open or tied to ground. |
| 30 | AISEN4 | input | Loop_A phase #4 current sense positive input, paired with AIREF4, used for channel current balancing, loadline regulation and overcurrent protection. |
| 31 | AIREF5 | input | Loop_A phase #5 current sense negative input, paired with AISEN5; unused pairs may be left open or tied to ground. |
| 32 | AISEN5 | input | Loop_A phase #5 current sense positive input, paired with AIREF5, used for channel current balancing, loadline regulation and overcurrent protection. |
| 33 | AIREF6 | input | Loop_A phase #6 current sense negative input, paired with AISEN6; unused pairs may be left open or tied to ground. |
| 34 | AISEN6 | input | Loop_A phase #6 current sense positive input, paired with AIREF6, used for channel current balancing, loadline regulation and overcurrent protection. |
| 35 | BVSEN | input | Loop_B positive voltage sense input for the remote sense amplifier (as AVSEN); if unused it may be grounded or left open. |
| 36 | BVREF | input | Loop_B negative voltage sense input paired with BVSEN; if unused it may be grounded or left open. |
| 37 | BIREF1 | input | Loop_B phase #1 current sense negative input, paired with BISEN1; may be left open or grounded if Loop_B is not used. |
| 38 | BISEN1 | input | Loop_B phase #1 current sense positive input, paired with BIREF1; may be left open or grounded if Loop_B is not used. |
| 39 | MP3 | bidirectional | Multi-purpose pin configurable as FAULT2 or SMBAlert#, and programmable as 3.3V CMOS, open drain, or analog. |
| 40 | MP4 | bidirectional | Multi-purpose pin configurable as FAULT2 or SMBAlert#, and programmable as 3.3V CMOS, open drain, or analog. |
| 41 | XADDR2 | input | Used together with XADDR1 to set the controller I2C address through an external resistor tied between this pin and GND. |
| 42 | BTSEN | input | Loop_B external temperature sense input (analog), referenced to the ATSEN description. |
| 43 | ATSEN | input | Loop_A external temperature sense input; may be left floating if the internal temperature sensor is selected or external temperature reporting is not required. |
| 44 | XADDR1 | input | Used together with XADDR2 to set the controller I2C address through an external resistor tied between this pin and GND. |
| 45 | VINSEN | input | VIN (+12V) voltage sense input used to guarantee a valid input voltage before startup (input undervoltage lockout), via a resistor divider or the PI sense network; may be grounded if unused. |
| 46 | IINSEN | input | Current sense input for PWR_IN calculation, driven from an external amplifier or PI sense network translating a precision sense resistor; may be grounded if unused. |
| 47 | VDD | power_in | 3.3V power supply input (3.0V min, 3.3V nom, 3.6V max) to the digital controller, to be decoupled with high quality 1.0µF + 0.1µF ceramic capacitors. |
| 48 | VD12 | power_out | Internally generated 1.2V supply for the digital core logic; do not apply voltage to or ground this pin, use only for 1.0µF + 0.1µF decoupling, and do not use it to drive external components. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | VQFN-48-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute max) | VDD | -0.3 | 4 | V | Note A | 3 | |
| VCLK, VDIO, VALRT# | VCLK, VDIO, VALRT# | -0.3 | 1.35 | V | 3 | ||
| AVSEN, BVSEN, CVSEN | AVSEN, BVSEN, CVSEN | -0.3 | 3.7 | V | Do not exceed VDD + 0.2V | 3 | |
| AVREF, BVREF, CVREF | AVREF, BVREF, CVREF | -0.3 | 0.5 | V | 3 | ||
| DCR current sense (ISENx, IREFx) | ISENx, IREFx | -0.3 | 3.7 | V | Do not exceed VDD + 0.2V | 3 | |
| Integrated current sense (ISENx, IREFx) | ISENx, IREFx | -0.3 | 2 | V | 3 | ||
| VD12 | VD12 | -1 | 1 | mA | Do not drive or load this pin | 3 | |
| All other pins | All other pins | -0.3 | 4 | V | Note A, Note B | 3 | |
| Junction temperature | TJ | -40 | 125 | C | 3 | ||
| Storage temperature | TSTG | -65 | 150 | C | 3 | ||
| Lead temperature | TLEAD | 300 | C | Soldering, 10 seconds | 3 | ||
| Supply voltage (recommended) | VDD | 3 | 3.3 | 3.6 | V | 3 | |
| Ambient temperature range | TA | -5 | 25 | 85 | C | Applicable to "PX…CDM" and "PX…CDN" devices only | 3 |
| Junction-to-ambient thermal resistance at 0 lfm (6mm x 6mm QFN) | JA(0) | 30.3 | C/W | at 0 lfm | 3 | ||
| Junction-to-ambient thermal resistance at 200 lfm (6mm x 6mm QFN) | JA(200) | 26.2 | C/W | at 200 lfm | 3 | ||
| Junction-to-ambient thermal resistance at 500 lfm (6mm x 6mm QFN) | JA(500) | 23.4 | C/W | at 500 lfm | 3 | ||
| Junction-to-case thermal resistance (6mm x 6mm QFN) | JC | 2.8 | C/W | 3 |
CAD (KiCad official)
- Symbol:
PXE1610CDN-G003 - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm - 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
pxe1610cdn-g003-etched.step/pxe1610cdn-g003-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pxe1610cdn-g003.step/pxe1610cdn-g003.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (20 pp, sha256
06de21df1d169910, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).