component
PUMH18
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PUMH18
Nexperia · Digital Transistors · SOT-363
PUMH18 from Nexperia, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND1 | power_in | Ground connection at the emitter of the TR1 NPN transistor; the datasheet gives no pin-specific limit for this pin. |
| 2 | I1 | input | Input at the base of TR1 with built-in 4.7 kΩ bias resistor R1 (R2 = 10 kΩ); device input voltage VI is rated -7 V to 20 V. |
| 3 | O2 | output | Output at the collector of TR2; device output current IO is rated at 100 mA maximum and VCEO at 50 V maximum. |
| 4 | GND2 | power_in | Ground connection at the emitter of the TR2 NPN transistor; the datasheet gives no pin-specific limit for this pin. |
| 5 | I2 | input | Input at the base of TR2 with built-in 4.7 kΩ bias resistor R1 (R2 = 10 kΩ); device input voltage VI is rated -7 V to 20 V. |
| 6 | O1 | output | Output at the collector of TR1; device output current IO is rated at 100 mA maximum and VCEO at 50 V maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-base voltage (open emitter) | VCBO | 50 | V | open emitter; per transistor | 3 | ||
| Collector-emitter voltage (open base) | VCEO | 50 | V | open base; per transistor | 3 | ||
| Emitter-base voltage (open collector) | VEBO | 7 | V | open collector; per transistor | 3 | ||
| Input voltage | VI | -7 | 20 | V | 3 | ||
| Output current | IO | 100 | mA | per transistor | 3 | ||
| Total power dissipation (per transistor) | Ptot | 200 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper, standard footprint | 3 | ||
| Total power dissipation (per device) | Ptot | 300 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper, standard footprint | 3 | ||
| Junction temperature | Tj | 150 | °C | 3 | |||
| Ambient temperature | Tamb | -65 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Thermal resistance junction to ambient (per transistor) | Rth(j-a) | 625 | K/W | in free air; FR4 PCB, single-sided copper, standard footprint | 4 | ||
| Thermal resistance junction to ambient (per device) | Rth(j-a) | 417 | K/W | in free air; FR4 PCB, single-sided copper, standard footprint | 4 | ||
| Collector-base breakdown voltage | V(BR)CBO | 50 | V | IC = 100 µA; IE = 0 A; Tamb = 25 °C | 5 | ||
| Collector-emitter breakdown voltage | V(BR)CEO | 50 | V | IC = 2 mA; IB = 0 A; Tamb = 25 °C | 5 | ||
| Collector-base cut-off current | ICBO | 100 | nA | VCB = 50 V; IE = 0 A; Tamb = 25 °C | 5 | ||
| Collector-emitter cut-off current | ICEO | 100 | nA | VCE = 30 V; IB = 0 A; Tamb = 25 °C | 5 | ||
| Collector-emitter cut-off current | ICEO | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C | 5 | ||
| Emitter-base cut-off current | IEBO | 600 | µA | VEB = 5 V; IC = 0 A; Tamb = 25 °C | 5 | ||
| DC current gain | hFE | 50 | VCE = 5 V; IC = 10 mA; Tamb = 25 °C | 5 | |||
| Collector-emitter saturation voltage | VCEsat | 100 | mV | IC = 10 mA; IB = 0.5 mA; Tamb = 25 °C | 5 | ||
| Off-state input voltage | VI(off) | 0.9 | 0.3 | V | VCE = 5 V; IC = 100 µA; Tamb = 25 °C | 5 | |
| On-state input voltage | VI(on) | 2.5 | 1.5 | V | VCE = 0.3 V; IC = 20 mA; Tamb = 25 °C | 5 | |
| Bias resistor 1 (input) | R1 | 3.3 | 4.7 | 6.1 | kΩ | 5 | |
| Bias resistor ratio | R2/R1 | 1.7 | 2.1 | 2.6 | 5 | ||
| Collector capacitance | Cc | 2.5 | pF | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C | 5 |
CAD (KiCad official)
- Symbol:
PUMH18 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
pumh18-etched.step/pumh18-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pumh18.step/pumh18.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (11 pp, sha256
02e44c508d98acd1, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PUMH18
**Nexperia** · Digital Transistors · SOT-363
PUMH18 from Nexperia, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND1 | power_in | Ground connection at the emitter of the TR1 NPN transistor; the datasheet gives no pin-specific limit for this pin. |
| 2 | I1 | input | Input at the base of TR1 with built-in 4.7 kΩ bias resistor R1 (R2 = 10 kΩ); device input voltage VI is rated -7 V to 20 V. |
| 3 | O2 | output | Output at the collector of TR2; device output current IO is rated at 100 mA maximum and VCEO at 50 V maximum. |
| 4 | GND2 | power_in | Ground connection at the emitter of the TR2 NPN transistor; the datasheet gives no pin-specific limit for this pin. |
| 5 | I2 | input | Input at the base of TR2 with built-in 4.7 kΩ bias resistor R1 (R2 = 10 kΩ); device input voltage VI is rated -7 V to 20 V. |
| 6 | O1 | output | Output at the collector of TR1; device output current IO is rated at 100 mA maximum and VCEO at 50 V maximum. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-base voltage (open emitter) | VCBO | | | 50 | V | open emitter; per transistor | 3 |
| Collector-emitter voltage (open base) | VCEO | | | 50 | V | open base; per transistor | 3 |
| Emitter-base voltage (open collector) | VEBO | | | 7 | V | open collector; per transistor | 3 |
| Input voltage | VI | -7 | | 20 | V | | 3 |
| Output current | IO | | | 100 | mA | per transistor | 3 |
| Total power dissipation (per transistor) | Ptot | | | 200 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper, standard footprint | 3 |
| Total power dissipation (per device) | Ptot | | | 300 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper, standard footprint | 3 |
| Junction temperature | Tj | | | 150 | °C | | 3 |
| Ambient temperature | Tamb | -65 | | 150 | °C | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Thermal resistance junction to ambient (per transistor) | Rth(j-a) | | | 625 | K/W | in free air; FR4 PCB, single-sided copper, standard footprint | 4 |
| Thermal resistance junction to ambient (per device) | Rth(j-a) | | | 417 | K/W | in free air; FR4 PCB, single-sided copper, standard footprint | 4 |
| Collector-base breakdown voltage | V(BR)CBO | 50 | | | V | IC = 100 µA; IE = 0 A; Tamb = 25 °C | 5 |
| Collector-emitter breakdown voltage | V(BR)CEO | 50 | | | V | IC = 2 mA; IB = 0 A; Tamb = 25 °C | 5 |
| Collector-base cut-off current | ICBO | | | 100 | nA | VCB = 50 V; IE = 0 A; Tamb = 25 °C | 5 |
| Collector-emitter cut-off current | ICEO | | | 100 | nA | VCE = 30 V; IB = 0 A; Tamb = 25 °C | 5 |
| Collector-emitter cut-off current | ICEO | | | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C | 5 |
| Emitter-base cut-off current | IEBO | | | 600 | µA | VEB = 5 V; IC = 0 A; Tamb = 25 °C | 5 |
| DC current gain | hFE | 50 | | | | VCE = 5 V; IC = 10 mA; Tamb = 25 °C | 5 |
| Collector-emitter saturation voltage | VCEsat | | | 100 | mV | IC = 10 mA; IB = 0.5 mA; Tamb = 25 °C | 5 |
| Off-state input voltage | VI(off) | | 0.9 | 0.3 | V | VCE = 5 V; IC = 100 µA; Tamb = 25 °C | 5 |
| On-state input voltage | VI(on) | 2.5 | 1.5 | | V | VCE = 0.3 V; IC = 20 mA; Tamb = 25 °C | 5 |
| Bias resistor 1 (input) | R1 | 3.3 | 4.7 | 6.1 | kΩ | | 5 |
| Bias resistor ratio | R2/R1 | 1.7 | 2.1 | 2.6 | | | 5 |
| Collector capacitance | Cc | | | 2.5 | pF | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C | 5 |
## CAD (KiCad official)
- Symbol: `PUMH18`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `pumh18-etched.step` / `pumh18-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pumh18.step` / `pumh18.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/PUMH18.pdf) (11 pp, sha256 `02e44c508d98acd1`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pumh18-datasheet.pdf)