PT8200 from PUOLOP, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VT	passive	Test pin (测试管脚) with no electrical limits or connection requirement stated in the datasheet.
2	GND	power_in	Battery cell negative terminal (电芯负极) and the reference node of the protection circuit, to which the charger/load negative is connected through the internal switch.
3	VDD	power_in	Power supply input for the IC; absolute maximum input voltage is -0.3 V to 6 V.
4	VM	passive	Negative terminal of the charger or load, connected to GND through an internal switch; absolute maximum input voltage is -6 V to 10 V.
5	VM	passive	Second VM pin, bonded to the same charger/load negative node as pin 4; absolute maximum input voltage is -6 V to 10 V.

Key specifications

Parameter	Value
Manufacturer	PUOLOP
Package	SOT-23-5L
Category	Power Management ICs
Pins	5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD pin input voltage		-0.3		6	V		3
VM pin input voltage		-6		10	V		3
Operating temperature		-40		85	℃		3
Maximum junction temperature				125	℃		3
Storage temperature		-55		150	℃		3
Power dissipation				0.4	W	25℃	3
Thermal resistance, junction to ambient	JA			250	℃/W		3
Overcharge detection voltage	VCU	4.25	4.3	4.35	V		3
Overcharge release voltage	VCL	4.05	4.1	4.15	V		3
Overdischarge detection voltage	VDL	2.32	2.4	2.48	V		3
Overdischarge release voltage	VDR	2.92	3	3.08	V		3
Charger detection voltage	VCHA	-0.1	-0.12	-0.15	V		3
Overcharge current detection	Iocc	2.8	3.5	4.3	A	Vdd=3.6V	3
Overdischarge current detection 1	IOV1	3.2	4	4.8	A	Vdd=3.6V	3
Overdischarge current detection 2	IOV2	5.6	7	8.4	A	Vdd=3.6V	3
Load short-circuit detection current	SHORT	12	15	18	A	Vdd=3.6V	3
Normal operating current	OPE	1.5	2.8	6	uA	Vdd=3.6V，VM=0V	3
Standby current	PDN	1	1.6	2.2	uA	Vdd=2V，VM floating	3
Equivalent on-resistance (internal MOSFET)	RDS	50	65	80	mΩ	Vdd=3.6V，IVM=1A	3
Over-temperature protection	OTP	125	140	155	℃		4
Over-temperature recovery	OTPR	100	115	130	℃		4
Overcharge current detection delay time	TOCC	6.4	8	9.6	ms	VDD=3.6V	4
Overcharge detection delay time	TCU	105	135	165	ms	VDD=3.6V~4.4V	4
Overdischarge detection delay time	TDL	28	35	33	ms	VDD=3.6V~2.0V	4
Overcurrent 1 detection delay time	TIOV1	6.4	8	9.6	ms	VDD=3.6V	4
Overcurrent 2 detection delay time	TIO21	0.8	1	1.2	ms	VDD=3.6V	4
Load short-circuit detection delay time	TSHORT	40	50	60	us	VDD=3.6V	4

CAD (KiCad official)

Symbol: PT8200
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5L (KiCad packages3D, STEP)
3D model files: pt8200-etched.step / pt8200-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pt8200.step / pt8200.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: PUOLOP datasheet (9 pp, sha256 f49006c3e83c7014, retrieved 2026-10-31, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

PT8200

Verified PT8200

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README