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PT6303SESOH-AC
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PowTech CR PowTech Shanghai Battery Management, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PT6303SESOH-AC
PowTech CR PowTech Shanghai · Battery Management · SOP-8
PT6303SESOH-AC from PowTech CR PowTech Shanghai, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Chip supply pin; the recommended supply voltage is 3.2 V to 15 V, and the absolute maximum VCC is VSS-0.3 V to VSS+25 V. |
| 2 | B3 | input | Positive input of the third cell and negative input of the stack's top cell voltage sense; cell input range is 2.0 V to 4.5 V recommended, and B3 is limited to VSS-0.3 V to VCC+0.3 V. |
| 3 | B2 | input | Negative input of the third cell and positive input of the second cell; B2-B1 and B3-B2 voltages are limited to a minimum of -5 V. |
| 4 | B1 | input | Negative input of the second cell and positive input of the first cell; B1 is limited to VSS-0.3 V to VCC+0.3 V. |
| 5 | VSS | power_in | Negative terminal of the first cell and the chip ground reference for the device. |
| 6 | LM | input | Multi-function pin for discharge over-current voltage sensing (PDOC1 at 50/75/100/150 mV, PDOC2 at 2x PDOC1, short-circuit at 4x PDOC1), load-open detection (VLMTH 0.75 V) and charger detection; its absolute range is VSS-0.3 V to VCC+0.3 V and it sinks up to 70 µA at VLM = 5 V. |
| 7 | DDR | output | Discharge MOSFET gate driver output that swings between VSS (off) and VCC (on), sourcing up to 3 mA and sinking up to 5 mA, with a voltage range of VSS-0.3 V to VCC+0.3 V. |
| 8 | CDR | output | Charge MOSFET gate driver output that is pulled up with 6 µA when the charge MOSFET is on, with a voltage range of VCC-25 V to VCC+0.3 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PowTech CR PowTech Shanghai |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC working voltage (VCC-GND) | VCC | 3.2 | 15 | V | VCC-GND | 5 | |
| Startup voltage (VCC rising edge) | VPOR | 3.4 | 3.8 | 4.2 | V | VCC rising edge | 5 |
| Cell voltage detection period | TSCN | 0.35 | 0.5 | 0.65 | S | 5 | |
| Cell overcharge detection voltage accuracy | VCOV | -25 | 25 | mV | Cell voltage rising, no protection event; VCOV 4.2-4.375 V selectable, 25mV/step | 5 | |
| Cell overcharge release voltage accuracy | VCOVR | -25 | 25 | mV | After COV event, cell voltage falling; VCOVR=VCOV-VΔCOV, VΔCOV 0-300 mV | 5 | |
| Cell over-discharge detection voltage accuracy | VCUV | -50 | 50 | mV | Cell voltage falling, no protection event; VCUV 2.3-2.9 V selectable, 0.2V/step | 5 | |
| Cell over-discharge release voltage accuracy | VCUVR | -80 | 80 | mV | After CUV event, cell voltage rising; VCUVR=VCUV+VΔCUV, VΔCUV 0.3-0.9 V | 5 | |
| Discharge overcurrent 1 detection voltage accuracy | VPDOC1 | -10 | 10 | mV | LM pin voltage rising; VPDOC1 50/75/100/150 mV selectable | 5 | |
| Discharge overcurrent 1 trigger delay | TPDOC1 | 0.7 | 1 | 1.3 | S | 5 | |
| Discharge overcurrent 2 detection voltage accuracy | VPDOC2 | -20 | 20 | mV | LM pin voltage rising; VPDOC2 = 2*VPDOC1 | 5 | |
| Short-circuit detection voltage accuracy | VPSC | -50 | 50 | mV | LM pin voltage rising; VPSC = 4*VPDOC1 | 5 | |
| Short-circuit trigger delay | TPSC | 200 | 250 | 300 | μS | 5 | |
| Cell input voltage (Cell1, Cell2, Cell3) | VCEL1-3 | 2 | 4.5 | V | 4 | ||
| Operating temperature | TOPT | -40 | 85 | ℃ | 4 | ||
| Supply voltage | VCC | 3.2 | 15 | V | 4 | ||
| Power dissipation | PD | 0.15 | W | 4 | |||
| Storage temperature | TSTG | -55 | 125 | ℃ | 4 |
CAD (KiCad official)
- Symbol:
PT6303SESOH-AC - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
pt6303sesoh-ac-etched.step/pt6303sesoh-ac-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pt6303sesoh-ac.step/pt6303sesoh-ac.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PowTech CR PowTech Shanghai datasheet (10 pp, sha256
14da6f637e8e3653, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PT6303SESOH-AC
**PowTech CR PowTech Shanghai** · Battery Management · SOP-8
PT6303SESOH-AC from PowTech CR PowTech Shanghai, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Chip supply pin; the recommended supply voltage is 3.2 V to 15 V, and the absolute maximum VCC is VSS-0.3 V to VSS+25 V. |
| 2 | B3 | input | Positive input of the third cell and negative input of the stack's top cell voltage sense; cell input range is 2.0 V to 4.5 V recommended, and B3 is limited to VSS-0.3 V to VCC+0.3 V. |
| 3 | B2 | input | Negative input of the third cell and positive input of the second cell; B2-B1 and B3-B2 voltages are limited to a minimum of -5 V. |
| 4 | B1 | input | Negative input of the second cell and positive input of the first cell; B1 is limited to VSS-0.3 V to VCC+0.3 V. |
| 5 | VSS | power_in | Negative terminal of the first cell and the chip ground reference for the device. |
| 6 | LM | input | Multi-function pin for discharge over-current voltage sensing (PDOC1 at 50/75/100/150 mV, PDOC2 at 2x PDOC1, short-circuit at 4x PDOC1), load-open detection (VLMTH 0.75 V) and charger detection; its absolute range is VSS-0.3 V to VCC+0.3 V and it sinks up to 70 µA at VLM = 5 V. |
| 7 | DDR | output | Discharge MOSFET gate driver output that swings between VSS (off) and VCC (on), sourcing up to 3 mA and sinking up to 5 mA, with a voltage range of VSS-0.3 V to VCC+0.3 V. |
| 8 | CDR | output | Charge MOSFET gate driver output that is pulled up with 6 µA when the charge MOSFET is on, with a voltage range of VCC-25 V to VCC+0.3 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PowTech CR PowTech Shanghai |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC working voltage (VCC-GND) | VCC | 3.2 | | 15 | V | VCC-GND | 5 |
| Startup voltage (VCC rising edge) | VPOR | 3.4 | 3.8 | 4.2 | V | VCC rising edge | 5 |
| Cell voltage detection period | TSCN | 0.35 | 0.5 | 0.65 | S | | 5 |
| Cell overcharge detection voltage accuracy | VCOV | -25 | | 25 | mV | Cell voltage rising, no protection event; VCOV 4.2-4.375 V selectable, 25mV/step | 5 |
| Cell overcharge release voltage accuracy | VCOVR | -25 | | 25 | mV | After COV event, cell voltage falling; VCOVR=VCOV-VΔCOV, VΔCOV 0-300 mV | 5 |
| Cell over-discharge detection voltage accuracy | VCUV | -50 | | 50 | mV | Cell voltage falling, no protection event; VCUV 2.3-2.9 V selectable, 0.2V/step | 5 |
| Cell over-discharge release voltage accuracy | VCUVR | -80 | | 80 | mV | After CUV event, cell voltage rising; VCUVR=VCUV+VΔCUV, VΔCUV 0.3-0.9 V | 5 |
| Discharge overcurrent 1 detection voltage accuracy | VPDOC1 | -10 | | 10 | mV | LM pin voltage rising; VPDOC1 50/75/100/150 mV selectable | 5 |
| Discharge overcurrent 1 trigger delay | TPDOC1 | 0.7 | 1 | 1.3 | S | | 5 |
| Discharge overcurrent 2 detection voltage accuracy | VPDOC2 | -20 | | 20 | mV | LM pin voltage rising; VPDOC2 = 2*VPDOC1 | 5 |
| Short-circuit detection voltage accuracy | VPSC | -50 | | 50 | mV | LM pin voltage rising; VPSC = 4*VPDOC1 | 5 |
| Short-circuit trigger delay | TPSC | 200 | 250 | 300 | μS | | 5 |
| Cell input voltage (Cell1, Cell2, Cell3) | VCEL1-3 | 2 | | 4.5 | V | | 4 |
| Operating temperature | TOPT | -40 | | 85 | ℃ | | 4 |
| Supply voltage | VCC | 3.2 | | 15 | V | | 4 |
| Power dissipation | PD | | | 0.15 | W | | 4 |
| Storage temperature | TSTG | -55 | | 125 | ℃ | | 4 |
## CAD (KiCad official)
- Symbol: `PT6303SESOH-AC`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `pt6303sesoh-ac-etched.step` / `pt6303sesoh-ac-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pt6303sesoh-ac.step` / `pt6303sesoh-ac.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [PowTech CR PowTech Shanghai datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884274271424512) (10 pp, sha256 `14da6f637e8e3653`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pt6303sesoh-ac-datasheet.pdf)