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pt5606-s

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JSMSEMI Isolators - Gate Drivers, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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PT5606-S

JSMSEMI · Isolators - Gate Drivers · SOP-8

PT5606-S from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side/logic supply. Recommended 10V to 20V, absolute max 25V. VCC UVLO+ ~8.9V, UVLO- ~8.2V. Quiescent current IQCC typ 120uA (max 240uA). Decouple to VSS with a local ceramic capacitor.
2 HIN input High-side logic signal input. CMOS/LSTTL compatible; VIH ≥ 2.5V, VIL ≤ 0.8V (with VCC = 10-20V). Drives high-side output HO through the level shifter. Input bias 5uA (typ) at 5V.
3 LIN input Low-side logic signal input. CMOS/LSTTL compatible; VIH ≥ 2.5V, VIL ≤ 0.8V (with VCC = 10-20V). Drives low-side output LO. Input bias 5uA (typ) at 5V.
4 COM power_in Low-side return / logic ground (VSS). All VCC-referenced input thresholds and low-side output are referenced to this pin. Datasheet pin-function table labels pin 4 as VSS while the SOP-8 top view labels it COM; they are the same node.
5 LO output Low-side gate-drive output, referenced to COM/VSS. Swings from 0V to VCC. Source current 300mA (typ), sink current 600mA (typ) with PW ≤ 10us. Turn-on/turn-off propagation delay ~130ns.
6 VS power_in High-side floating return / bootstrap ground. Connect to the source of the high-side power MOSFET (switching node). Recommended operating range -9V to +700V; can tolerate transient -50V pulses ≤50ns. Allowable dVs/dt is 50 V/ns.
7 HO output High-side gate-drive output, referenced to VS. Swings from VS to VB. Source 300mA / sink 600mA (PW ≤ 10us). Propagation delay ~130ns, matched to LO within 50ns.
8 VB power_in High-side floating bootstrap supply. Connect a bootstrap capacitor (CBOOT) between VB and VS; feed via a bootstrap diode from VCC. Recommended VB = VS+10V to VS+20V. Absolute max 725V referenced to VSS. IQBS typ 50uA.

Key specifications

Parameter Value
Manufacturer JSMSEMI
Package SOP-8
Category PMIC
Pins 8

Ordering variants

  • PT5606-SS

CAD (KiCad official)

  • Symbol: PT5606-S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: pt5606-s-etched.step / pt5606-s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pt5606-s.step / pt5606-s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JSMSEMI datasheet (None pp, sha256 bfbc2d47d0a3cf26, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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PCB Footprint

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Datasheet

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