# PT4308

**PTC Princeton Tech** · RF Transceiver ICs · SOP-8

PT4308 from PTC Princeton Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | Ground reference for the device; the datasheet asks that the larger ground plane be placed as close as possible to all VSS pins. |
| 2 | ANT | input | RF input connected to the antenna through an L-type matching network (L1/C1) to present 50 Ohm; ESD protection is rated at better than 4 kV HBM, 400 V MM and 1 kV CDM. |
| 3 | VREG | power_out | Regulated core voltage output from the on-chip regulator, which requires a bypass capacitor C2 placed as close as possible to the pin. |
| 4 | VDD5 | power_in | 5 V regulator input that accepts a supply range of 2.1 V to 5.5 V (5.0 V nominal) and should incorporate series-R, shunt-C filtering; absolute maximum is -0.3 V to 6 V. |
| 5 | EN | input | Chip enable: tie HIGH for normal operation (VIH minimum 0.8 x VDD5) and LOW for standby (VIL maximum 0.2 x VDD5), where standby current is 1 µA maximum. |
| 6 | DO | output | Data output with VOH minimum 0.9 x VDD5 at -1 µA and VOL maximum 0.1 x VDD5 at +1 µA, and a rise/fall time of about 2 µs at 15 pF load. |
| 7 | CTH | bidirectional | Connection for the data slicing threshold capacitor CTH, which works with the on-chip 32.5 kΩ RTH to set the slicing level time constant; a squelch resistor may also be connected here. |
| 8 | XIN | input | Reference oscillator input for the 13.598 MHz crystal (CLoad 220 pF in the reference design), requiring a minimum oscillation swing of 300 mVpP. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | PTC Princeton Tech |
| Package | SOP-8 |
| Category | RF And Wireless |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD5 | 2.1 | 5 | 5.5 | V | Supply voltage applied to VDD5 pin only | 12 |
| Standby Current | ISTBY |  |  | 1 | μA | CE = LOW | 12 |
| Operating Frequency Range | fRF | 390 | 433.92 | 480 | MHz |  | 12 |
| Maximum Receiver Input Level | PRF,MAX | -20 | -15 |  | dBm |  | 12 |
| Data Rate | DRATE |  | 2 | 10 | Kb／s |  | 12 |
| System Start-Up Time | TSTUP |  | 2 | 3 | ms | With fast start-up circuit | 12 |
| LO Leakage | LLO |  |  | -80 | dBm | Measured at antenna input | 12 |
| Receive Modulation Duty Cycle | DUTY | 20 |  | 80 | % |  | 12 |
| CTH Leakage Current | IZCTH | -100 |  | 100 | nA | TA = +85 °C | 12 |
| VCO Frequency Range | fVCO | 370 |  | 500 | MHz |  | 12 |
| Reference Signal Voltage Swing | VREF | 0.3 |  | 2 | V | Peak-to-peak voltage (VPP) | 12 |
| Supply Voltage Range | VDD5 | -0.3 |  | 6 | V |  | 11 |
| Analog I/O Voltage |  | -0.3 |  | 3 | V |  | 11 |
| Digital I/O Voltage |  | -0.3 |  | 6 | V |  | 11 |
| Operating Temperature Range | TA | -40 |  | 85 | °C |  | 11 |
| Storage Temperature Range | TSTG | -40 |  | 125 | °C |  | 11 |
| ESD Rating (HBM) | VESD (HBM) | -4000 |  | 4000 | V |  | 11 |
| ESD Rating (MM) | VESD (MM) | -400 |  | 400 | V |  | 11 |
| ESD Rating (CDM) | VESD (CDM) | -1000 |  | 1000 | V |  | 11 |
| From Chip Conjunction Dissipation to Package Surface | Rjc |  | 1 | 1.8 | °C／W |  | 11 |
| Current Consumption | IDD5 |  | 4.3 |  | mA |  | 12 |
| Sensitivity (ASK) | SIN |  | -114 |  | dBm | ASK2, DRATE = 2 Kb／s, Peak power level | 12 |
| Sensitivity (OOK) | SIN |  | -108 |  | dBm | OOK, DRATE = 2 Kb／s, Peak power level | 12 |
| Image Rejection Ratio | IRR |  | 25 |  | dB |  | 12 |
| IF Center Frequency | fIF |  | 1.236 |  | MHz |  | 12 |
| IF Bandwidth | BWIF |  | 380 |  | KHz |  | 12 |
| RSSI Slope | SLRSSI |  | 8 |  | mV／dB |  | 12 |
| Post-Demodulator Filter Bandwidth | BWDF |  | 5 |  | KHz |  | 12 |
| Reference Frequency | fREFOSC |  | 13.598 |  | MHz |  | 12 |
| Divider Ratio | DIV |  | 32 |  |  |  | 12 |
| Output Current (source) | IOUT |  | 480 |  | μA | Source current at 0.8 × VDD5 | 12 |
| Output Current (sink) | IOUT |  | 600 |  | μA | Sink current at 0.2 × VDD5 | 12 |
| Output Rise/Fall Times | tR/tF |  | 2 |  | μs | DO pin, CLOAD = 15 pF | 12 |
| From Chip Conjunction Dissipation to External Environment | Rja |  | 37.15 |  | °C／W | TA = 27 °C | 11 |

## CAD (KiCad official)

- Symbol: `PT4308`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `pt4308-etched.step` / `pt4308-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pt4308.step` / `pt4308.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [PTC Princeton Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884852427276288) (15 pp, sha256 `f3ac3a7eb2a87770`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pt4308-datasheet.pdf)