main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 11d ago
viewers pt4302-x: viewers · Ray 11d ago
package.json Publish 0.1.0 · Ray 11d ago
page.json Set visibility: public · Ray 11d ago
pt4302-x-etched.glb Publish 0.1.0 · Ray 11d ago
pt4302-x-etched.step pt4302-x: factory component page (tier=lcsc) · Ray 11d ago
pt4302-x-hero.glb pt4302-x: hero GLB from the etched model (keeps the MPN mark) · Ray 11d ago
pt4302-x-hero.overlay.json Publish 0.1.0 · Ray 11d ago
pt4302-x.glb Publish 0.1.0 · Ray 11d ago
pt4302-x.kicad_mod Publish 0.1.0 · Ray 11d ago
pt4302-x.kicad_sym Publish 0.1.0 · Ray 11d ago
pt4302-x.lbr Publish 0.1.0 · Ray 11d ago
pt4302-x.step Publish 0.1.0 · Ray 11d ago
README.md Publish 0.1.0 · Ray 11d ago

PT4302-X

PTC Princeton Tech · RF Transceiver ICs · SSOP-16-150mil

PT4302-X from PTC Princeton Tech, in a SSOP-16-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSSLO power_in Ground pin for the local oscillator circuit (本振电路接地端).
2 VSSRF power_in Ground pin for the RF circuit (射频电路接地端).
3 ANT input Antenna input; the L-type match network brings it near 50 Ω, and the datasheet recommends a series inductor/capacitor match with an optional ESD-protection inductor.
4 VRF power_in RF regulated supply pin (射频稳压电源); the internal regulator powers the whole chip, so this pin must be tied to the other supply pins and bypassed.
5 MIXOUT output Mixer output (混频器输出端) with a specified output impedance of 300-360 Ω.
6 VBB power_in Baseband regulated supply pin (基频稳压电源); tie to the other supply pins and add proper bypass capacitance.
7 IFIN input IF amplifier input (中频放大器输入端) with a specified input impedance of 300-360 Ω, designed to interface with the external 10.7 MHz ceramic filter.
8 VDD5 power_in 5 V input supply pin (5 V 输入电源); the only supply pin that connects externally, with a 2.4 V to 5.5 V operating range and an absolute maximum of -0.3 V to 6 V.
9 VSSBB power_in Ground pin for the baseband circuit (基频电路接地端).
10 SELB input Data filter bandwidth select pin B (数据滤波器频宽选择 Pin B), which together with SELA sets the demodulator bandwidth; logic high/low thresholds are 0.8 VDD5 minimum and 0.2 VDD5 maximum.
11 SELA input Data filter bandwidth select pin A (数据滤波器频宽选择 Pin A), which together with SELB sets the demodulator bandwidth; logic high/low thresholds are 0.8 VDD5 minimum and 0.2 VDD5 maximum.
12 CE input Power enable pin (电源作动开关); high turns the chip on and low (0 V) turns it off, with off-state leakage below 1 μA.
13 DO output Data demodulator output (数据解调输出); push-pull output with a typical rise/fall time of 10 μs at 15 pF load.
14 CTH bidirectional Data demodulator threshold capacitor pin (数据解调器准位电容); an external capacitor (typically ±20% X7R) sets the threshold time constant together with the internal ~25 kΩ RTH.
15 VLO power_in Local oscillator circuit supply pin (本振电路电源); tie to the other supply pins and add bypass capacitance, and it is also the pin the datasheet uses as the internal supply for the CTH noise-suppression resistor example.
16 REFOSC input Reference oscillator pin (晶振输入) for a series-resonant crystal to ground or an external AC-coupled signal, with 300 mVpp minimum crystal amplitude or 0.3 to 1.5 Vpp external drive.

Key specifications

Parameter Value
Manufacturer PTC Princeton Tech
Package SSOP-16-150mil
Category RF And Wireless
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage (VDD5 only connected) VDD5 2.4 5 5.5 V Only VDD5 connected 10
Input voltage VDD5 absolute maximum VDD5 -0.3 6 V 9
Analog pin voltage range -0.3 3 V 9
Digital pin voltage range -0.3 6 V 9
Operating temperature range TA -40 85 °C 9
Storage temperature range TSTG -55 125 °C 9
Consumption current at fRF=315 MHz IDD5 2.7 3 mA fRF=315 MHz 10
Consumption current at fRF=434 MHz IDD5 2.9 3.2 mA fRF=434 MHz 10
Standby current ISTBY 1 μA CE="Low" 10
Frequency range fRF 250 500 MHz 10
Maximum input signal PRF,MAX -20 -15 dBm 10
Receiver sensitivity (ASK) SIN -112 -109 dBm ASK (AM 99% square wave), DRate=2 Kb/s, 315 MHz, BER=1e-3 10
Receiver sensitivity (OOK) SIN -106 -103 dBm OOK, DRate=2 Kb/s, 315 MHz, BER=1e-3 10
Receiver sensitivity (ASK) SIN -111 -108 dBm ASK (AM 99% square wave), DRate=2 Kb/s, 434 MHz, BER=1e-3 10
Receiver sensitivity (OOK) SIN -105 -102 dBm OOK, DRate=2 Kb/s, 434 MHz, BER=1e-3 10
Data rate DRATE 2 10 Kb/s 10
LO leakage measured at antenna LLO -80 dBm Measured at antenna pin 10
System startup time TSTUP 5 8 ms RF input power=-60 dBm 10
RF voltage gain at 315 MHz GVRF 40 43 46 dB Matched to 50 Ω, 315 MHz 10
RF voltage gain at 434 MHz GVRF 39 42 45 dB Matched to 50 Ω, 434 MHz 10
Noise figure at 315 MHz NFRF 5.7 6.3 dB Matched to 50 Ω, 315 MHz 10
Noise figure at 434 MHz NFRF 6.1 6.7 dB Matched to 50 Ω, 434 MHz 10
Mixer output impedance ZOUT,MIXER 300 330 360 Ω 10
IF frequency fIF 10.7 MHz 10
IF bandwidth BWIF 180 KHz Depends on external 10.7 MHz ceramic filter bandwidth 10
IF input impedance ZIN,IF 300 330 360 Ω 10
RSSI slope SLRSSI 9.5 11.5 13.5 mV/dB 10
Demodulator bandwidth (SELA=SELB=High) BWDF 0.9 KHz SELA = SELB = "High" 10
Demodulator bandwidth (SELA=High, SELB=Low) BWDF 1.8 KHz SELA = "High"; SELB = "Low" 10
Demodulator bandwidth (SELA=Low, SELB=High) BWDF 3.6 KHz SELA = "Low"; SELB = "High" 10
Demodulator bandwidth (SELA=SELB=Low) BWDF 7.2 KHz SELA = SELB = "Low" 10
CTH leakage current IZCTH -100 100 nA TA = +85 °C 10
Reference frequency fREFOSC 7 16 MHz 10
Reference signal voltage amplitude VREF 0.3 1.5 V Peak-to-peak voltage (VPP) 10
VCO frequency range fVCO 220 550 MHz 10
Divider ratio DIV 32 10
High-level input voltage VIN,High 0.8 VDD5 CE, SELA, SELB pins 10
Low-level input voltage VIN,Low 0.2 VDD5 CE, SELA, SELB pins 10
Output current (push-pull) IOUT 20 μA DO pin, push-pull 10
High-level output voltage VOUT,High 0.9 VDD5 DO pin, IOUT = -1 μA 10
Low-level output voltage VOUT,Low 0.1 VDD5 DO pin, IOUT = +1 μA 10
DO output rise/fall time tR/tF 10 μs DO pin, CLOAD = 15 pF 10
Thermal resistance junction to ambient Rja 37.15 °C/W TA=27 °C; four-layer copper-clad test board, 1.15 W dissipation 9
Thermal resistance junction to package surface Rjc 1 1.8 °C/W 9

CAD (KiCad official)

  • Symbol: PT4302-X
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16-150mil (KiCad packages3D, STEP)
  • 3D model files: pt4302-x-etched.step / pt4302-x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pt4302-x.step / pt4302-x.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PTC Princeton Tech datasheet (14 pp, sha256 23fc7b3f7f6689a6, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF