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PT24C02

Public Made by Adom

by adom

PUOLOP EEPROM, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs pt24c02: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pt24c02: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
pt24c02-etched.fit.json pt24c02: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
pt24c02-etched.glb pt24c02: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
pt24c02-etched.step pt24c02: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
pt24c02.glb Publish 0.1.0 · Ray 1mo ago
pt24c02.kicad_mod Publish 0.1.0 · Ray 1mo ago
pt24c02.kicad_sym Publish 0.1.0 · Ray 1mo ago
pt24c02.lbr Publish 0.1.0 · Ray 1mo ago
pt24c02.step Publish 0.1.0 · Ray 1mo ago
README.md pt24c02: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago

PT24C02

PUOLOP · EEPROM · SOP-8

PT24C02 from PUOLOP, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Device address input bit 0. Hard-wired to VCC or GND to set the I2C slave address for the PT24C02 (three address bits A2/A1/A0 allow up to eight devices on one bus).
2 A1 input Device address input bit 1. Hard-wired to VCC or GND to set the I2C slave address for the PT24C02.
3 A2 input Device address input bit 2. Hard-wired to VCC or GND to set the I2C slave address for the PT24C02.
4 GND power_in Ground reference (0 V) for the device.
5 SDA bidirectional Serial data. Open-drain bidirectional pin for I2C data transfer; requires an external pull-up resistor and may be wire-ORed with other open-drain devices on the bus.
6 SCL input Serial clock input. Positive-edge clocks data into the EEPROM; negative-edge clocks data out. Requires an external pull-up resistor.
7 WP input Write Protect. When tied to GND, normal read/write operations are allowed. When tied to VCC, the full 2K array is write-protected in hardware.
8 VCC power_in Supply voltage input. Operating range 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer PUOLOP
Package SOP-8
Category Memory
Pins 8

CAD (KiCad official)

  • Symbol: PT24C02
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: pt24c02-etched.step / pt24c02-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pt24c02.step / pt24c02.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUOLOP datasheet (14 pp, sha256 46f82af43f3e981c, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF