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PT2466

PTC Princeton Tech · Brushed DC Motor Drivers · SOP-8

PT2466 from PTC Princeton Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VM	power_in	Motor power supply, 0 to 11 V recommended operating range with a 12 V absolute maximum rating; bypass to GND with a low-ESR ceramic capacitor, typically 0.1 µF, placed close to the pin.
2	OUT1	output	Motor output 1 from the H-bridge, with HS+LS on-resistance of 280 mΩ typical and a 1.8 A maximum DC drive current.
3	OUT2	output	Motor output 2 from the H-bridge, with HS+LS on-resistance of 280 mΩ typical and a 1.8 A maximum DC drive current.
4	GND	power_in	Ground reference for the device; VM and VCC should be bypassed to this pin with a thick trace or ground-plane connection.
5	IN2	input	PWM input 2 controlling OUT2 in the IN-IN bridge control scheme, with logic high at 0.5×VCC minimum, logic low at 0.3×VCC maximum, and a 100 kΩ internal pulldown.
6	IN1	input	PWM input 1 controlling OUT1 in the IN-IN bridge control scheme, with logic high at 0.5×VCC minimum, logic low at 0.3×VCC maximum, and a 100 kΩ internal pulldown.
7	nSLEEP	input	Sleep mode input; driving it logic low puts the H-bridge FETs into Hi-Z sleep, and driving it logic high returns the part to active operation after a 5 µs maximum wake time, with a 100 kΩ internal pulldown.
8	VCC	power_in	Logic power supply, 1.8 V to 5 V recommended, with an undervoltage lockout at 1.7 V falling and 1.8 V rising; bypass to GND with low-ESR ceramic capacitors.

Key specifications

Parameter	Value
Manufacturer	PTC Princeton Tech
Package	SOP-8
Category	Motor Driver ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Motor power supply voltage	VM	-0.3		12	V		6
Logic power supply voltage	VCC	-0.3		5.5	V		6
Operating temperature	Top	-40		150	°C		6
Storage temperature	Tstg	-40		150	°C		6
Operation humidity		20		85	%		6
Storage humidity		20		90	%		6
ESD HBM, all pins		-4		4	KV	HBM; printed as ±4 KV	6
ESD MM, all pins		-0.4		0.4	KV	MM; printed as ±0.4 KV	6
ESD CDM		-1.5		1.5	KV	CDM per ANSI/ESDA/JEDEC JS-002-2014; printed as ±1.5 KV	6
VM motor power supply voltage	VM	0		11	V		6
VCC logic power supply voltage	VCC	1.8		5	V		6
Motor peak current	IOUT	0		1.8	A		6
Externally applied PWM frequency	fPWM	0		250	KHz		6
Logic level input voltage	VLOGIC	0		5	V		6
Operating ambient temperature	TA	-40		85	°C		6
VM coast current	IVM1		65	90	µA	VM=5V ; VCC=3V ; No PWM ; Coast Mode	7
VM F/R current	IVM2		300	500	µA	VM=5V ; VCC=3V ; No PWM ; Forward/Reverse Mode	7
VM brake current	IVM3		65	90	µA	VM=5V ; VCC=3V ; No PWM ; Brake Mode	7
VM PWM current	IVM4		240	400	µA	VM=5V ; VCC=3V ; PWM=50KHz	7
VM sleep current	IVMQ			5	nA	VM=5V ; VCC=3V ; nSLEEP=0	7
VCC coast current	IVCC1		380	500	µA	VM=5V ; VCC=3V ; No PWM ; Coast Mode	7
VCC F/R current	IVCC2		450	650	µA	VM=5V ; VCC=3V ; No PWM ; Forward/Reverse Mode	7
VCC brake current	IVCC3		480	650	µA	VM=5V ; VCC=3V ; No PWM ; Brake Mode	7
VCC PWM current	IVCC4		450	650	µA	VM=5V ; VCC=3V ; PWM=50KHz	7
VCC sleep current	IVCCQ			2	nA	VM=5V ; VCC=3V ; nSLEEP=0	7
Input logic low current	IIL			5	µA	VIN=0V	7
Input logic high current	IIH			50	µA	VIN=3.3V	7
Pulldown resistance (IN1, IN2, nSLEEP)	RPD		100		KΩ		7
HS + LS FET on-resistance	rDS(ON)		280		mΩ	VM=5V ; VCC=3V ; Io=800mA ; Tj=25℃	7
Off-state leakage current	IOFF			5	nA	VOUT=0V	7
VCC under-voltage lockout, falling	VUVLO		1.7		V	VCC falling	7
VCC under-voltage lockout, rising	VUVLO		1.8		V	VCC rising	7
Over-current protection trip level	IOCP	1.9		3.5	A		7
Over-current retry time	tRETRY		1		mS		7
Thermal shutdown temperature	TTSD		160		℃	Die temperature	7
Output enable time	t1			0.8	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8
Output disable time	t2			0.8	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8
Delay time, INx high to OUTx high	t3			0.7	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8
Delay time, INx low to OUTx low	t4			0.7	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8
Output rise time	t5			0.5	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8
Output fall time	t6			0.5	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8
Wake time, nSLEEP rising edge to part active	twake			5	µS	TA=25℃, VM=5V, VCC=3V, RL=20Ω	8

CAD (KiCad official)

Symbol: PT2466
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: pt2466-etched.step / pt2466-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pt2466.step / pt2466.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: PTC Princeton Tech datasheet (13 pp, sha256 98c8250a59dc6ca8, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF