# PSM712-LF-T7-JSM

**JSMSEMI** · ESD And Surge Protection (TVS/ESD) · SOT-23

PSM712-LF-T7-JSM from JSMSEMI, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O 1 | passive | Protected I/O line 1 with a 12V TVS to pin 3 (VRWM 12V max, VBR 13.3V min at 1mA) and a 7V TVS from pin 3 (VRWM 7V max, VBR 7.5V min). |
| 2 | I/O 2 | passive | Protected I/O line 2 with a 12V TVS to pin 3 (VRWM 12V max, VBR 13.3V min at 1mA) and a 7V TVS from pin 3 (VRWM 7V max, VBR 7.5V min). |
| 3 | GND | power_in | Common ground reference for both TVS channels, connected to circuit ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOT-23 |
| Category | Circuit Protection |
| Pins | 3 |

## CAD (KiCad official)

- Symbol: `PSM712-LF-T7-JSM`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `psm712-lf-t7-jsm-etched.step` / `psm712-lf-t7-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `psm712-lf-t7-jsm.step` / `psm712-lf-t7-jsm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602989046213849088) (4 pp, sha256 `12b8a2e2f8fcb9b7`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/psm712-lf-t7-jsm-datasheet.pdf)