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PMV65XPER

TECH PUBLIC · MOSFETs · SOT-23

PMV65XPER from TECH PUBLIC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; the pin diagram puts G at the bottom-left, which is pin 1 in the outline drawing. Rated ±10 V gate-source, with a built-in ESD protection diode.
2 S passive Source; the pin diagram puts S at the bottom-right, which is pin 2 in the outline drawing. Continuous drain current is -3 A.
3 D passive Drain; the pin diagram puts D at the top, which is pin 3 in the outline drawing. Rated -20 V drain-source, with continuous drain current of -3 A and pulsed drain current of -13.2 A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: PMV65XPER
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pmv65xper-etched.step / pmv65xper-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pmv65xper.step / pmv65xper.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (3 pp, sha256 67b4b1f675c3cd72, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF