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Contents

README

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PMV50EPEA

TECH PUBLIC · MOSFETs · SOT-23

PMV50EPEA from TECH PUBLIC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; gate-source voltage limit is ±10 V, VGS(th) is -0.35 V min to -0.9 V max at ID=-250µA, with ESD rating 2500V HBM.
2 S passive Source of the P-channel MOSFET; continuous drain current is -4 A and body-diode forward current is -4 A.
3 D passive Drain, the single lead on one side of the package; drain-source voltage is -20 V, continuous drain current -4 A and pulsed -30 A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: PMV50EPEA
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pmv50epea-etched.step / pmv50epea-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pmv50epea.step / pmv50epea.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (3 pp, sha256 b7f24f7e5985ae6c, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF