PM8804TR

{
  "slug": "pm8804tr",
  "version": "0.1.0",
  "type": "component",
  "description": "STMicroelectronics Power Over Ethernet (PoE) Controllers, TQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "pm8804tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "pm8804tr.kicad_sym",
    "pm8804tr.kicad_mod",
    "pm8804tr.glb",
    "pm8804tr.step",
    "pm8804tr.lbr",
    "docs/hero.png",
    "docs/pm8804tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pm8804tr-hero.glb",
    "pm8804tr-hero.overlay.json"
  ],
  "component": {
    "mpn": "PM8804TR",
    "manufacturer": "STMicroelectronics",
    "package": "TQFN-16-EP(3x3)",
    "pin_count": 17,
    "category": "Power Management (PMIC)",
    "subcategory": "Power Over Ethernet (PoE) Controllers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589784620615950336",
    "parts": {
      "symbol": "pm8804tr.kicad_sym",
      "footprint": "pm8804tr.kicad_mod",
      "model_3d": "pm8804tr-hero.glb",
      "model_3d_plain": "pm8804tr.glb",
      "model_3d_step": "pm8804tr-etched.step",
      "model_3d_step_plain": "pm8804tr.step",
      "lbr": "pm8804tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2971161",
      "digikey": "497-18075-2-ND",
      "mouser": "511-PM8804TR"
    },
    "distributor_check": {
      "checked_at": "2026-10-10T15:52:50Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "497-18075-2-ND",
        "status": "found",
        "lifecycle": "Discontinued at DigiKey"
      },
      "mouser": {
        "pn": "511-PM8804TR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog signal ground for all sensitive analog circuitry, to be connected to PGND in a star configuration at a single connection point close to pin 10."
      },
      {
        "number": "2",
        "name": "SS",
        "type": "bidirectional",
        "description": "Soft-start set pin; a capacitor from SS to AGND sets the soft-start time, with stable ceramic capacitors recommended and typical CSS values of 10 nF to 100 nF."
      },
      {
        "number": "3",
        "name": "DT",
        "type": "passive",
        "description": "Delay time set pin; a resistor from DT to AGND sets the GAT1-to-GAT2 delay between 10 ns and 200 ns (RDT 20 kΩ to 390 kΩ), and this pin cannot be left open."
      },
      {
        "number": "4",
        "name": "FSW",
        "type": "passive",
        "description": "Switching frequency set pin; an external resistor from FSW to AGND sets the oscillator frequency in the range 100 kHz to 1 MHz (RFSW 20 kΩ to 250 kΩ)."
      },
      {
        "number": "5",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected; leave unconnected on layout, which increases the creepage distance between VIN and PGD and the other device pins."
      },
      {
        "number": "6",
        "name": "PGD",
        "type": "input",
        "description": "Active-high power-good signal; a low-to-high transition enables converter operation, and a high-to-low transition during normal operation stops the converter with GAT1 and GAT2 frozen in their default state."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected; leave unconnected on layout, which increases the creepage distance between VIN and PGD and the other device pins."
      },
      {
        "number": "8",
        "name": "VIN",
        "type": "power_in",
        "description": "High-voltage input, typically the rectified PoE input bridge voltage referred to AGND; operating input range 10 V to 75 V and absolute maximum -0.3 V to 85 V."
      },
      {
        "number": "9",
        "name": "GAT1",
        "type": "output",
        "description": "Main gate driver output of the PWM controller, with 1 A peak sink and 0.8 A peak source capability for driving the main MOSFET."
      },
      {
        "number": "10",
        "name": "PGND",
        "type": "power_in",
        "description": "System power and analog ground and power ground for the gate drivers, to be connected to AGND at a single star point close to this pin."
      },
      {
        "number": "11",
        "name": "GAT2",
        "type": "output",
        "description": "Secondary gate driver output for active clamp or synchronous rectification, with 1 A peak sink and 0.8 A peak source capability; its delay relative to GAT1 is set by DT and its operation is selected by MODE."
      },
      {
        "number": "12",
        "name": "VC",
        "type": "power_out",
        "description": "Output of the internal high-voltage start-up regulator, regulated to 8 V typical and to be filtered with a ceramic capacitor to AGND (2.2 µF, 25 V typical), with absolute maximum rating of -0.3 V to 16 V."
      },
      {
        "number": "13",
        "name": "MODE",
        "type": "input",
        "description": "Operation mode select; tie to AGND to turn off GAT2 and disable soft-stop, and leave open to enable both since it is internally pulled up, with the logic threshold at 0.7 V."
      },
      {
        "number": "14",
        "name": "CS",
        "type": "input",
        "description": "Current sense input for current-mode control and overcurrent protection; GAT1 switches low for cycle-by-cycle limiting when CS exceeds 0.25 V, with the blanking period applied after GAT1 turns high."
      },
      {
        "number": "15",
        "name": "CTL",
        "type": "input",
        "description": "Input of the PWM comparator with a useful range between 0.7 V and 1.7 V and an integrated 3.3 kΩ pull-up that can also bias an optocoupler transistor."
      },
      {
        "number": "16",
        "name": "BLK",
        "type": "passive",
        "description": "Blanking time set pin; a resistor from BLK to AGND sets the current-sense masking time between 10 ns and 200 ns (RBLK 20 kΩ to 390 kΩ), and this pin cannot be left open."
      },
      {
        "number": "17",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Table 2 assigns pin 9 = GAT1, pin 10 = PGND, pin 11 = GAT2, but Section 6.2 text says 'pin 11 and pi; The exposed pad is listed as '- EP' in Table 2 with no numeric pin number, so it is reported as 'EP'; Table 2 lists pins 5 and 7 together as NC; both are reported individually as unconnected per that ro",
          "exposed pad 17 added from the footprint",
          "dropped thermal pad ['EP'] absent from footprint"
        ],
        "pages_sent": 27,
        "cost_usd": 0.0884,
        "at": "2026-10-10T15:52:36"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589784620615950336",
        "pages": 27,
        "sha256": "10b1af36939006fc",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "pm8804tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          3.0,
          0.785
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-10-10",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pm8804tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          3.0,
          0.785
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6be1bc391ba76db6c7ebfc810dc1bd2d872b9efcdadd2f32ed530cc596b1e973",
        "checked": "2026-10-10",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}