component
PM8804TR
Public Made by Adomby adom
STMicroelectronics Power Over Ethernet (PoE) Controllers, TQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PM8804TR
STMicroelectronics · Power Over Ethernet (PoE) Controllers · TQFN-16-EP(3x3)
PM8804TR from STMicroelectronics, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog signal ground for all sensitive analog circuitry, to be connected to PGND in a star configuration at a single connection point close to pin 10. |
| 2 | SS | bidirectional | Soft-start set pin; a capacitor from SS to AGND sets the soft-start time, with stable ceramic capacitors recommended and typical CSS values of 10 nF to 100 nF. |
| 3 | DT | passive | Delay time set pin; a resistor from DT to AGND sets the GAT1-to-GAT2 delay between 10 ns and 200 ns (RDT 20 kΩ to 390 kΩ), and this pin cannot be left open. |
| 4 | FSW | passive | Switching frequency set pin; an external resistor from FSW to AGND sets the oscillator frequency in the range 100 kHz to 1 MHz (RFSW 20 kΩ to 250 kΩ). |
| 5 | NC | unconnected | Not connected; leave unconnected on layout, which increases the creepage distance between VIN and PGD and the other device pins. |
| 6 | PGD | input | Active-high power-good signal; a low-to-high transition enables converter operation, and a high-to-low transition during normal operation stops the converter with GAT1 and GAT2 frozen in their default state. |
| 7 | NC | unconnected | Not connected; leave unconnected on layout, which increases the creepage distance between VIN and PGD and the other device pins. |
| 8 | VIN | power_in | High-voltage input, typically the rectified PoE input bridge voltage referred to AGND; operating input range 10 V to 75 V and absolute maximum -0.3 V to 85 V. |
| 9 | GAT1 | output | Main gate driver output of the PWM controller, with 1 A peak sink and 0.8 A peak source capability for driving the main MOSFET. |
| 10 | PGND | power_in | System power and analog ground and power ground for the gate drivers, to be connected to AGND at a single star point close to this pin. |
| 11 | GAT2 | output | Secondary gate driver output for active clamp or synchronous rectification, with 1 A peak sink and 0.8 A peak source capability; its delay relative to GAT1 is set by DT and its operation is selected by MODE. |
| 12 | VC | power_out | Output of the internal high-voltage start-up regulator, regulated to 8 V typical and to be filtered with a ceramic capacitor to AGND (2.2 µF, 25 V typical), with absolute maximum rating of -0.3 V to 16 V. |
| 13 | MODE | input | Operation mode select; tie to AGND to turn off GAT2 and disable soft-stop, and leave open to enable both since it is internally pulled up, with the logic threshold at 0.7 V. |
| 14 | CS | input | Current sense input for current-mode control and overcurrent protection; GAT1 switches low for cycle-by-cycle limiting when CS exceeds 0.25 V, with the blanking period applied after GAT1 turns high. |
| 15 | CTL | input | Input of the PWM comparator with a useful range between 0.7 V and 1.7 V and an integrated 3.3 kΩ pull-up that can also bias an optocoupler transistor. |
| 16 | BLK | passive | Blanking time set pin; a resistor from BLK to AGND sets the current-sense masking time between 10 ns and 200 ns (RBLK 20 kΩ to 390 kΩ), and this pin cannot be left open. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
PM8804TR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
pm8804tr-etched.step/pm8804tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pm8804tr.step/pm8804tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (27 pp, sha256
10b1af36939006fc, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PM8804TR
**STMicroelectronics** · Power Over Ethernet (PoE) Controllers · TQFN-16-EP(3x3)
PM8804TR from STMicroelectronics, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog signal ground for all sensitive analog circuitry, to be connected to PGND in a star configuration at a single connection point close to pin 10. |
| 2 | SS | bidirectional | Soft-start set pin; a capacitor from SS to AGND sets the soft-start time, with stable ceramic capacitors recommended and typical CSS values of 10 nF to 100 nF. |
| 3 | DT | passive | Delay time set pin; a resistor from DT to AGND sets the GAT1-to-GAT2 delay between 10 ns and 200 ns (RDT 20 kΩ to 390 kΩ), and this pin cannot be left open. |
| 4 | FSW | passive | Switching frequency set pin; an external resistor from FSW to AGND sets the oscillator frequency in the range 100 kHz to 1 MHz (RFSW 20 kΩ to 250 kΩ). |
| 5 | NC | unconnected | Not connected; leave unconnected on layout, which increases the creepage distance between VIN and PGD and the other device pins. |
| 6 | PGD | input | Active-high power-good signal; a low-to-high transition enables converter operation, and a high-to-low transition during normal operation stops the converter with GAT1 and GAT2 frozen in their default state. |
| 7 | NC | unconnected | Not connected; leave unconnected on layout, which increases the creepage distance between VIN and PGD and the other device pins. |
| 8 | VIN | power_in | High-voltage input, typically the rectified PoE input bridge voltage referred to AGND; operating input range 10 V to 75 V and absolute maximum -0.3 V to 85 V. |
| 9 | GAT1 | output | Main gate driver output of the PWM controller, with 1 A peak sink and 0.8 A peak source capability for driving the main MOSFET. |
| 10 | PGND | power_in | System power and analog ground and power ground for the gate drivers, to be connected to AGND at a single star point close to this pin. |
| 11 | GAT2 | output | Secondary gate driver output for active clamp or synchronous rectification, with 1 A peak sink and 0.8 A peak source capability; its delay relative to GAT1 is set by DT and its operation is selected by MODE. |
| 12 | VC | power_out | Output of the internal high-voltage start-up regulator, regulated to 8 V typical and to be filtered with a ceramic capacitor to AGND (2.2 µF, 25 V typical), with absolute maximum rating of -0.3 V to 16 V. |
| 13 | MODE | input | Operation mode select; tie to AGND to turn off GAT2 and disable soft-stop, and leave open to enable both since it is internally pulled up, with the logic threshold at 0.7 V. |
| 14 | CS | input | Current sense input for current-mode control and overcurrent protection; GAT1 switches low for cycle-by-cycle limiting when CS exceeds 0.25 V, with the blanking period applied after GAT1 turns high. |
| 15 | CTL | input | Input of the PWM comparator with a useful range between 0.7 V and 1.7 V and an integrated 3.3 kΩ pull-up that can also bias an optocoupler transistor. |
| 16 | BLK | passive | Blanking time set pin; a resistor from BLK to AGND sets the current-sense masking time between 10 ns and 200 ns (RBLK 20 kΩ to 390 kΩ), and this pin cannot be left open. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## CAD (KiCad official)
- Symbol: `PM8804TR`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `pm8804tr-etched.step` / `pm8804tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pm8804tr.step` / `pm8804tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589784620615950336) (27 pp, sha256 `10b1af36939006fc`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pm8804tr-datasheet.pdf)