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PM8800A

STMicroelectronics · AC-DC Controllers & Regulators · HTSSOP-16-EP

PM8800A from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RT input Oscillator timing resistor pin to AGND that sets the oscillator frequency and also accepts narrow ac-coupled synchronization pulses from an external clock.
2 SS passive Soft-start input where an external capacitor to AGND and an internal 10 µA current source set the soft-start ramp rate and the hiccup timer on overcurrent.
3 AUXII input Auxiliary source enable pin used to power up the DC/DC section only from the external source; the resistor to the external source sets whether it prevails over PoE (absolute max -0.3 to 100 V to AGND).
4 VIN power_in System high potential input, the most positive input potential, being the diode OR of the PoE line and auxiliary sources (absolute max -0.3 to 100 V to VSS).
5 RCLASS passive Classification resistor pin; connect a classification programming resistor between this pin and VSS (absolute max -0.3 to 3.6 V to VSS).
6 AUXI_IRL input In-rush current limit and auxiliary source enable pin; a resistor to VSS sets the inrush current limit, and pulling it up to the auxiliary source changes the UVLO settings (absolute max -0.3 to 100 V to VSS).
7 DCCL passive DC current limit pin where a resistor to VSS sets the interface current limit, possibly above the IEEE 802.3af limit, and which is left open for standard 802.3af applications.
8 VSS power_in System low potential input.
9 GND power_in System return for the PWM converter and drain of the internal hot-swap power MOSFET (absolute max -0.3 to 100 V to VSS).
10 GD output Output of the PWM controller, the external power MOSFET gate driver output (absolute max -0.3 to 15 V to AGND).
11 VCC power_out Output of the internal high voltage regulator, which switches off when an auxiliary winding raises this pin above the regulation set point (absolute max -0.3 to 15 V to AGND).
12 nPGD output Active-low power good signal whose high-to-low transition indicates inrush is complete, the hot-swap MOSFET is fully closed and the SMPS is activated (absolute max -0.3 to 15 V to AGND).
13 CS input Current sense input for current mode control and overcurrent protection; GD switches low cycle-by-cycle if CS exceeds 0.5 V, with leading edge blanking.
14 COMP output Error amplifier output and PWM input, with an internal 2.5 kΩ pull-up that may bias an opto-coupler transistor.
15 VFB input Inverting input of the internal error amplifier with the non-inverting input at an internal 1.25 V reference; ground to AGND if not used.
16 AGND power_in Analog PWM supply return for sensitive analog circuitry including the SMPS current limit circuit; must be connected to GND to improve noise immunity.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package HTSSOP-16-EP
Category Power Management ICs
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Max thermal resistance junction to ambient RthJA 50 °C/W Package mounted on 4 layers 35 micron demoboard 8
Maximum junction temperature TMAX 150 °C 8
Storage temperature min TSTG -40 150 °C 8
Junction temperature range TJ -40 125 °C 8
Operative temperature range TA -40 85 °C 8
VIN, GND to VSS -0.3 100 V 9
AUXI_IRL to VSS -0.3 100 V 9
DCCL, RCLASS to VSS -0.3 3.6 V 9
AUXII to AGND -0.3 100 V 9
COMP, SS to AGND -0.3 3.6 V 9
VFB, RT, CS to AGND -0.3 3.6 V 9
VCC, GD to AGND -0.3 15 V 9
nPGD to AGND -0.3 15 V 9
GND to AGND -0.3 0.3 V 9
Signature resistance 23.5 24.5 25.5 kΩ 10
Signature disable classification turn on 10.5 11.5 12.5 V VIN rising 10
Classification turn-off 21.5 23 24.5 V VIN rising 10
RCLASS voltage during classification 1.37 1.4 1.43 V 10
UVLO release VUVLO_R 37 38.5 40 V VIN rising 10
UVLO lock-out VUVLO_F 30 31.5 33.5 V VIN falling 10
MOSFET resistance RDSON 0.5 1 Ω 10
Default in-rush current limit 120 140 160 mA VIN > 30 V 10
Default in-rush current limit 220 250 280 mA 15 V < VIN < 30 V 10
Default in-rush current limit 390 440 490 mA 1.5 V < VIN < 15 V 10
Adjustable in-rush current limit 120 140 160 mA RAUXI_IRL = 82 kΩ 10
Default DC current limit 390 440 490 mA 10
Adjustable DC current limit precision -15 15 % RDCLL = From 15.4 kΩ to 82 kΩ 10
Hot-swap VDS 1.45 1.6 1.75 V VDS falling 11
nPGD current source 25 30 35 µA 11
nPGD pull down resistance 0.5 V nPGD low; I = -5 mA 11
nPGD threshold 1.7 2 2.3 V nPGD rising 11
AUXI_IRL UVLO release 15 16 17 V VIN rising 11
AUXI_IRL UVLO lock-out 11.5 12.5 13.5 V VIN falling 11
AUX II Bias voltage 0.85 1.1 1.4 V IAUXII = 0 to -250 µA 11
AUX II Lower threshold current 20 35 50 µA 11
AUX II Upper threshold current 80 100 120 µA 11
Oscillator free running frequency fosc 85 100 115 kHz RT = open 12
Oscillator frequency fosc 210 240 270 kHz RT = 88 kΩ 12
Oscillator frequency fosc 385 440 495 kHz RT = 33 kΩ 12
EA input voltage VEA 1.21 1.25 1.29 V FB = COMP 12
COMP Sink current capability -8 -15 mA COMP to GND 12
Soft start current charging ISS 7 10 13 µA Charging 12
Soft start current discharging ISS -7 -10 -13 µA Discharging 12
SS voltage 2.1 2.3 2.5 V After soft start 12
Cycle by cycle current limit threshold voltage 0.44 0.5 0.56 V 12
Minimum duty cycle 0 % 12
Maximum duty cycle 80 83 % 12
Output low 0.25 0.5 V IGD = -100 mA 12
VCC Internal default VCC 8 8.3 8.6 V VIN = 48 V; VCC = open 13
VCC Current capability 10 mA VIN = 48 V; GD = open 13
VCC UVLO release wrt VCC -400 -50 mV VCC rising; wrt VCC 13
VCC UVLO lock-out 6.4 6.7 7.1 V VCC falling 13
IIN VIN supply current IIN 3 mA VIN = 48 V; VCC = 10 V 10
ICC VCC supply current ICC 4 mA VCC = 10 V 13

CAD (KiCad official)

  • Symbol: PM8800A
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: pm8800a-etched.step / pm8800a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pm8800a.step / pm8800a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (35 pp, sha256 2e57c2a0bb56d01b, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF