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PL9405
Public Made by Adomby adom
POWLICON DC-DC Converters, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPL9405
POWLICON · DC-DC Converters · QFN-48(6x6)
PL9405 from POWLICON, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST1 | passive | Bootstrap pin for the high-side MOSFET driver 1, referenced to SW1. |
| 2 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 3 | VBAT | power_in | Battery-side VBAT pin with a 3.6 V to 32 V input range; the pin-table text reads 'Connect to the VBUS rail', which conflicts with the pin name (see review_required). |
| 4 | CSP1 | input | Positive input of the input-side current sense, paired with CSN1 for average input current limiting against a 40 mV reference. |
| 5 | CSN1 | input | Negative input of the input-side current sense; shorting CSP1 to CSN1 disables the average current loop. |
| 6 | EN | input | Logic high above the 1.2 V operating threshold enables the converter; below the 1.1 V standby threshold only the LDO remains active, and the pin is pulled up to 4 V internally through 2 MΩ. |
| 7 | PGND | power_in | Power ground for the power stage, to be connected to AGND at the thermal pad. |
| 8 | CELLS | input | Resistor divider between VDD and GND programs the battery cell count from 1 to 6 cells. |
| 9 | OTG | input | Logic low selects battery charging mode and connection to LDO selects battery discharging mode; the OTG high threshold is 1.2 V with 200 mV hysteresis. |
| 10 | TS | input | Battery temperature sense input; a voltage divider sets the protection trip point in charging or discharging mode. |
| 11 | VDD | power_out | 5.4 V supply for the PL9405 control core. |
| 12 | VADJ | input | Accepts a 0-2 V analog voltage or PWM signal to program VREF; connecting it to VDD forces VREF to 2 V. |
| 13 | IADJ | input | Accepts a 0-2 V analog voltage or PWM signal to program IREF; connecting it to VDD forces IREF to 2 V. |
| 14 | VSET | input | Resistor to GND selects battery cell type (4.2 V, 4.35 V, 4.4 V or 4.5 V) in charging mode, and in discharging mode with OTG above 1.2 V its voltage follows the CSP2-CSN2 difference. |
| 15 | IREF | power_out | Reference voltage for the input and output current limiting loop. |
| 16 | VREF | power_out | Reference voltage for the voltage control loop, 2 V in discharging mode and 1.8 V in charging mode when VADJ is tied to VDD. |
| 17 | BRCOM | output | Battery internal-resistance compensation pin whose voltage is proportional to the CSP1-CSN1 difference, with a resistor to GND programming the compensation. |
| 18 | LDO | power_out | Low quiescent current 5 V / 55 mA LDO powered from VBAT that stays active to supply the system MCU when EN is low. |
| 19 | STAT | output | Charging status output in charging mode (OTG low) and power-good output in discharging mode (OTG high). |
| 20 | AGND | power_in | Analog ground, to be connected to PGND at the thermal pad under the IC. |
| 21 | FREQ | input | Connecting to GND sets 150 kHz and connecting to VDD sets 300 kHz; a divider between VDD and GND sets 600 kHz or 1200 kHz. |
| 22 | COMP | passive | Error amplifier output of the control loop. |
| 23 | VREG | input | Resistor divider programs the VBUS regulation voltage; when VBUS is pulled down to this setpoint in charging mode, the loop reduces charge current, and it is inactive in discharging mode. |
| 24 | FB2 | input | VBUS voltage feedback input regulated to 2 V in discharging mode through a resistor divider from VBUS to GND. |
| 25 | CSN2 | input | Negative input of the output-side current sense, paired with CSP2. |
| 26 | CSP2 | input | Positive input of the output-side current sense, paired with CSN2; shorting CSP2 to CSN2 disables the average current loop. |
| 27 | VBUS | power_in | Connect to the VBUS rail, with a 3.6 V to 32 V operating range. |
| 28 | HG2 | output | High-side MOSFET gate driver output 2, capable of 2 A source and 2 A sink peak current. |
| 29 | BST2 | passive | Bootstrap pin for the high-side driver 2, referenced to SW2. |
| 30 | PGND | power_in | Power ground for the power stage. |
| 31 | SW2 | passive | Switching node 2 of the power stage. |
| 32 | LG2 | output | Low-side MOSFET gate driver output 2, capable of 2 A source and 2 A sink peak current. |
| 33 | SW1 | passive | Switching node 1 of the power stage. |
| 34 | SW1 | passive | Switching node 1 of the power stage. |
| 35 | SW1 | passive | Switching node 1 of the power stage. |
| 36 | VCC | power_out | 6.6 V supply for the high-side and low-side gate drivers. |
| 37 | PGND | power_in | Power ground for the power stage. |
| 38 | PGND | power_in | Power ground for the power stage. |
| 39 | PGND | power_in | Power ground for the power stage. |
| 40 | PGND | power_in | Power ground for the power stage. |
| 41 | PGND | power_in | Power ground for the power stage. |
| 42 | SW1 | passive | Switching node 1 of the power stage. |
| 43 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 44 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 45 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 46 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 47 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 48 | D1 | bidirectional | Power node of VBAT connected to the battery port; it is the power output of the converter in charging mode and the power input in discharging mode. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | POWLICON |
| Package | QFN-48(6x6) |
| Category | Power Supply Chip |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VBAT battery voltage | 3.6 | 32 | V | 5 | |||
| VBUS bus line voltage | 3.6 | 32 | V | 5 | |||
| Operation threshold (EN UVLO) | VEN_UV | 1.1 | 1.2 | 1.3 | V | 5 | |
| High side MOS on resistance | RDSon_HS | 9 | 10 | mΩ | VCC=6.6V | 6 | |
| Low side MOS on resistance | RDSon_LS | 9 | 10 | mΩ | VCC=6.6V | 6 | |
| Input voltages VBAT, VBUS | 3.6 | 32 | V | 4 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 4 | ||
| VBAT, VBUS, CSN1, CSN2, CSP1, CSP2, SW1, SW2, D1 to GND | -0.3 | 40 | V | 4 | |||
| BST1 to SW1 | -0.3 | 7 | V | 4 | |||
| HG2, BST2 to SW2 | -0.3 | 7 | V | 4 | |||
| LG2, VCC to GND | -0.3 | 7 | V | 4 | |||
| CSP1 to CSN1 | -0.3 | 0.6 | V | 4 | |||
| CSP2 to CSN2 | -0.3 | 0.6 | V | 4 | |||
| VBAT to CSP1, CSN1 | -0.3 | 0.6 | V | 4 | |||
| VBUS to CSP2, CSN2 | -0.3 | 0.6 | V | 4 | |||
| Other pins to GND | -0.3 | 6 | V | 4 | |||
| Storage temperature range | TST | -65 | 150 | °C | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Lead temperature | TL | 260 | °C | 4 | |||
| ESD HBM Human body model | VESD | 2 | kV | HBM, Human body model | 4 | ||
| Junction to ambient thermal resistance (QFN6X6-48) | θJA | 58 | °C/W | Measured on approximately 1 inch square of 1 oz copper | 4 | ||
| Junction to case thermal resistance (QFN6X6-48) | θJC | 5 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
PL9405 - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm - 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
pl9405-etched.step/pl9405-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pl9405.step/pl9405.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: POWLICON datasheet (17 pp, sha256
aed439ba506a8969, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).