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PL8405Q

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POWLICON DC-DC Converters, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PL8405Q

POWLICON · DC-DC Converters · QFN-48(6x6)

PL8405Q from POWLICON, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST1 passive Boost pin for the high side MOSFET driver; BST to SW absolute maximum is -0.3 V to 7 V.
2 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
3 VBAT power_in Battery-side supply pin with a 4.5 V to 32 V battery voltage range in the electrical characteristics; the pin description text reads 'Connect to the VBUS rail'.
4 CSP1 input Positive input of the input current sense; CSP1 to CSN1 absolute maximum is -0.3 V to 0.6 V.
5 CSN1 input Minus input of the input current sense; CSP1 to CSN1 absolute maximum is -0.3 V to 0.6 V.
6 EN input Logic high enables the converter (operation threshold 1.1 V to 1.3 V); logic low disables everything except the LDO.
7 PGND power_in Power ground.
8 CELLS input Connect a resistor divider between VDD and GND to program the number of battery cells (1 to 6).
9 OTG input Connect to GND for battery charging mode and to VDD for battery discharging mode; OTG high threshold is 1.2 V.
10 TS input Battery temperature sense input, used with a voltage divider to set the protection trigger point.
11 VDD power_out 5.4 V power supply for the PL8405Q control core when VBAT is 15 V.
12 VADJ input Accepts a 0-2 V analog voltage or PWM signal to program the VREF reference; connecting it to VDD forces VREF to 2 V.
13 IADJ input Accepts a 0-2 V analog voltage or PWM signal to program the IREF reference; connecting it to VDD forces IREF to 2 V.
14 VSET passive A resistor to GND selects the battery cell type (4.2 V, 4.35 V, 4.4 V or 4.5 V) when OTG is low; above 1.2 V on OTG it carries a voltage proportional to the CSP2-CSN2 difference.
15 IREF output Reference voltage for the input and output current limiting loop.
16 VREF power_in Reference voltage for the voltage control loop, 2 V in discharge mode and 1.8 V in charge mode when VADJ is tied to VDD.
17 BRCOM output Battery internal resistance compensation pin whose voltage is proportional to the CSP1-CSN1 difference for charging current monitoring.
18 LDO power_out Low quiescent current 5 V/55 mA LDO powered from VBAT that supplies the system MCU and stays active when EN is low.
19 STAT output Charging status display when OTG is low and power good signal when OTG is high.
20 AGND power_in Analog ground; connect PGND and AGND together at the thermal pad under the IC.
21 FREQ input Switching frequency select: GND gives 150 kHz, VDD gives 300 kHz, and a resistor divider gives 600 kHz or 1200 kHz.
22 COMP passive Error amplifier output.
23 VREG input Resistor divider programs the VBUS regulation voltage; the VREG loop reduces charging current when VBUS is pulled down to the VREG setpoint of 1.2 V in charge mode.
24 FB2 input VBUS voltage feedback that regulates to 2 V in discharge mode through a resistor divider between VBUS and GND.
25 CSN2 input Minus input of the output current sense; CSP2 to CSN2 absolute maximum is -0.3 V to 0.6 V.
26 CSP2 input Positive input of the output current sense; CSP2 to CSN2 absolute maximum is -0.3 V to 0.6 V.
27 VBUS power_in Connect to the VBUS rail; VBUS operating range is 2 V to 30 V in the electrical characteristics.
28 NC unconnected Not connected.
29 NC unconnected Not connected.
30 PGND power_in Power ground.
31 NC unconnected Not connected.
32 NC unconnected Not connected.
33 SW1 output Switching point 1 of the power stage; SW absolute maximum is -0.3 V to 40 V.
34 SW1 output Switching point 1 of the power stage; SW absolute maximum is -0.3 V to 40 V.
35 SW1 output Switching point 1 of the power stage; SW absolute maximum is -0.3 V to 40 V.
36 VCC power_out 6.6 V power supply for the high side and low side gate drivers.
37 PGND power_in Power ground.
38 PGND power_in Power ground.
39 PGND power_in Power ground.
40 PGND power_in Power ground.
41 PGND power_in Power ground.
42 SW1 output Switching point 1 of the power stage; SW absolute maximum is -0.3 V to 40 V.
43 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
44 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
45 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
46 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
47 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
48 D1 bidirectional Power node of VBAT that connects to the battery input port, working as converter output when charging and input when discharging.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer POWLICON
Package QFN-48(6x6)
Category Power Supply Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute max: VBAT, VBUS, CSN1, CSN2, CSP1, CSP2, SW to GND -0.3 40 V 4
Absolute max: BST to SW -0.3 7 V 4
Absolute max: VCC to GND -0.3 7 V 4
Absolute max: CSP1 to CSN1 -0.3 0.6 V 4
Absolute max: CSP2 to CSN2 -0.3 0.6 V 4
Absolute max: VBAT to CSP1, CSN1 -0.3 0.6 V 4
Absolute max: VBUS to CSP2, CSN2 -0.3 0.6 V 4
Absolute max: Other pins to GND -0.3 6 V 4
Storage temperature range TST -65 150 °C 4
Junction temperature TJ 150 °C 4
Lead temperature TL 260 °C 4
ESD HBM VESD 2 kV Human body model 4
Input voltages VBAT, VBUS (recommended operating) VBAT, VBUS 3.6 32 V 4
Operating junction temperature range TJ -40 125 °C 4
Battery voltage VBAT 4.5 32 V 5
Bus line voltage VBUS 2 30 V 5
EN operation threshold VEN_UV 1.1 1.2 1.3 V Operation Threshold 5
VBAT shutdown current IQ_VBAT 15 uA EN=0V, VBAT=7.2V 5
VBAT supply current 1000 uA No Switching, FB=2.1V 5
VBUS shutdown current IQ_VBUS 15 uA EN=0V, VBUS=7.2V 5
VBUS supply current 1200 uA No Switching, battery fully charged 5
VCC driver power supply voltage VVCC 6.6 V VBAT =15V 5
VDD control core power supply voltage VVDD 5.4 V VBAT =15V 5
LDO output voltage VLDO 5 V VBAT =15V 5
LDO output current ILDO 55 mA VLDO =5V 5
VBAT UVLO rising VBAT_UV 3.5 V 5
VBAT UVLO hysteresis 300 mV 5
VBUS UVLO rising VBUS_UV 3.5 V 5
VBUS UVLO hysteresis 300 mV 5
EN hysteresis VEN_UV 200 mV Hysteresis 5
OTG high voltage threshold VTH_OTG 1.2 V 5
OTG hysteresis VHY_OTG 200 mV 5
VREF voltage in discharge mode VVREF_Dischg 2 V VADJ connected to VDD 5
VREF voltage in charge mode VVREF_chg 1.8 V VADJ connected to VDD 5
Trickle charge threshold VTH_TRKL 3 V VBAT voltage 5
Trickle charge hysteresis VHY_TRKL 0.5 V VBAT voltage 5
Battery recharge voltage VRECHAG 4 V 5
Battery full charge voltage VBAT_FULL 4.2 V VVSET :0.4-0.9V Rset:220k 5
Battery full charge voltage VBAT_FULL 4.35 V VVSET :0.9-1.9V Rset:430k 5
Battery full charge voltage VBAT_FULL 4.4 V VVSET :1.9-5.5V, short VSET pin to VDD. 5
Battery full charge voltage VBAT_FULL 4.5 V VVSET :0-0.4V, short VSET pin to GND. 5
VREG charge input regulation voltage VREG 1.2 V 5
VFB regulation voltage in discharging mode VFB 2 V FB voltage 5
Error amplifier gm GmEA 450 uS 5
COMP sink current ISINK 15 uA VFB=VREF+100mV 5
COMP source current ISOURCE 20 uA VFB=VREF-100mV 5
FB bias current IFB 100 nA FB2 in regulation 5
Switching frequency FSW 150 KHz FREQ 0-0.4V, short FREQ pin to GND. 5
Switching frequency FSW 300 KHz FREQ 1.8-5.4V, short FREQ pin to VDD. 5
Switching frequency FSW 600 KHZ FREQ 0.4-0.85V 5
Switching frequency FSW 1200 KHZ FREQ 0.85-1.8V 5
Battery average current limit, discharging mode ICCLIM_BAT 80 mV VCSP1-VCSN1, discharging mode 6
Battery average current limit, charging mode ICCLIM_BAT 40 mV VCSP1-VCSN1, charging mode 6
Bus average current limit, discharging mode ICCLIM_BUS 40 mV VCSP2-VCSN2, discharging mode 6
Bus average current limit, charging mode ICCLIM_BUS 80 mV VCSP2-VCSN2, charging mode 6
Output over voltage threshold VOVP 110 % 6
Output under voltage threshold VUVP 50 % 6
VPWM low voltage VTH_VADJ 0.4 V Note 4 6
VPWM high voltage VTH_VADJ 2.5 V Note 4 6
IPWM low voltage VTH_IADJ 0.4 V Note 4 6
IPWM high voltage VTH_IADJ 2.5 V Note 4 6
Thermal shutdown threshold TSD 150 °C Note 4 6
Thermal shutdown hysteresis THYS 20 °C Note 4 6

CAD (KiCad official)

  • Symbol: PL8405Q
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: pl8405q-etched.step / pl8405q-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pl8405q.step / pl8405q.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: POWLICON datasheet (14 pp, sha256 a32a5014920fede9, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF