# PL8322

**POWLICON** · DC-DC Converters · ESOP-8

PL8322 from POWLICON, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | power_out | Boot-strap pin: connect a 0.1µF or greater ceramic capacitor between SW and BST to power the high-side gate driver. |
| 2 | VIN | power_in | Power input supplied from a 6.5V to 36V source, to be bypassed to GND with a large capacitor plus at least 0.1uF ceramic placed close to the VIN and GND pins. |
| 3 | SW | output | Power switching pin connected to the inductor switching node. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | FB | input | Feedback input sensing the output voltage through a resistor divider to ground, with the datasheet noting it is a sensitive node to keep away from SW and BST and recommending a 47pF capacitor to GND; the internal reference is 1.2V. |
| 6 | IADJ | passive | Resistor from IADJ to GND sets the load current limit and line drop compensation (typical range 10k-50k per Section 9.4). |
| 7 | EN | input | Enable digital input: drive high to turn the regulator on and low to turn it off; internally pulled to VIN through a large resistor, with an internal threshold of 1V. |
| 8 | SS | passive | Soft-start programming pin where a capacitor sets the soft-start time. |
| 9 | EPAD | power_in | Exposed pad serving as power ground that must be connected to the PCB ground for full-load operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | POWLICON |
| Package | ESOP-8 |
| Category | Power Supply Chip |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND input voltage | VIN | -0.3 |  | 36 | V |  | 2 |
| VSS to GND | VSS | -0.3 |  | 6 | V |  | 2 |
| VEN to GND | VEN | -0.3 |  | 6 | V |  | 2 |
| VFB to GND | VFB | -0.3 |  | 6 | V |  | 2 |
| VIADJ to GND | VIADJ | -0.3 |  | 6 | V |  | 2 |
| VBST to VSW | VBST | -0.3 |  | 6 | V |  | 2 |
| VSW to GND | VSW | -1 |  |  | V |  | 2 |
| Storage temperature range | TST | -65 |  | 150 | °C |  | 3 |
| Junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Lead temperature | TL |  |  | 260 | °C |  | 3 |
| ESD HBM | VESD |  |  | 2 | kV | Human body model | 3 |
| ESD MM | VESD |  |  | 500 | V | Charger device model | 3 |
| VIN to GND input voltage (operating) | VIN | 6.5 |  | 36 | V |  | 3 |
| FB input voltage | FB | -0.3 |  | 6 | V |  | 3 |
| EN input voltage | EN | -0.3 |  | 6 | V |  | 3 |
| Output voltage | VOUT | 0.5 |  |  | V |  | 3 |
| Output current | IOUT | 0 |  | 3.1 | A |  | 3 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 3 |
| Junction to ambient thermal resistance (ESOP-8) | θJA |  | 56 |  | °C/W | Measured on approximately 1" square of 1 oz copper (Note 3) | 3 |
| Junction to case thermal resistance (ESOP-8) | θJC |  | 45 |  | °C/W |  | 3 |
| High-side switch on-resistance | RDS(ON)_H |  | 76 |  | mΩ | IOUT = 1A, VOUT = 3.3V | 4 |
| Low-side switch on-resistance | RDS(ON)_L |  | 52 |  | mΩ | IOUT = 1A, VOUT = 3.3V | 4 |
| Minimum input voltage for startup | VUVLO_up |  | 6.5 |  | V |  | 4 |
| VUVLO_down | VUVLO_down |  | 6 |  | V |  | 4 |
| VUVLO_hys | VUVLO_hys |  | 0.5 |  | V |  | 4 |
| Operating quiescent current | IQ-NONSW |  | 1 |  | mA | VFB =1.2V | 4 |
| Buck oscillator frequency | Foscb |  | 100 |  | kHz |  | 4 |
| Feedback voltage | VFB |  | 1.2 |  | V |  | 4 |
| Maximum duty cycle | Dmax |  | 95 |  | % | Guaranteed by design, not tested in production (Note 4) | 4 |
| Minimum on time | Ton |  | 200 |  | ns | Guaranteed by design, not tested in production (Note 4) | 4 |
| Upper switch current limit | Iocl_hs |  | 5.5 |  | A | Minimum Duty Cycle | 4 |
| Lower switch current limit | Iocl_ls |  | 4.5 |  | A | From Drain to Source | 4 |
| Input over voltage protection | Vinovp |  | 33 |  | V |  | 4 |
| Thermal shutdown | Thsd |  | 155 |  | °C | Guaranteed by design, not tested in production (Note 4) | 4 |
| Thermal shutdown hysteresis | Thsdhys |  | 15 |  | °C | Guaranteed by design, not tested in production (Note 4) | 4 |
| Hiccup duty cycle | Dhiccup |  | 10 |  | % | Guaranteed by design, not tested in production (Note 4) | 4 |

## CAD (KiCad official)

- Symbol: `PL8322`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `pl8322-etched.step` / `pl8322-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pl8322.step` / `pl8322.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [POWLICON datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893363882381312) (15 pp, sha256 `6e735715b7cbd555`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pl8322-datasheet.pdf)