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Ray Publish 0.1.0 11f478c 8h ago

PJM09N40PA

PJSEMI · MOSFETs · SOP-8

PJM09N40PA from PJSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Source passive Source terminal of the N-channel MOSFET, with gate-source voltage rated at ±20 V absolute maximum.
2 Source passive Source terminal of the N-channel MOSFET, with gate-source voltage rated at ±20 V absolute maximum.
3 Source passive Source terminal of the N-channel MOSFET, with gate-source voltage rated at ±20 V absolute maximum.
4 Gate input Gate control terminal, with gate-source voltage rated at ±20 V and gate threshold voltage of 1.0 to 2.5 V.
5 Drain passive Drain terminal of the N-channel MOSFET, rated at 40 V drain-source voltage and 9 A continuous drain current.
6 Drain passive Drain terminal of the N-channel MOSFET, rated at 40 V drain-source voltage and 9 A continuous drain current.
7 Drain passive Drain terminal of the N-channel MOSFET, rated at 40 V drain-source voltage and 9 A continuous drain current.
8 Drain passive Drain terminal of the N-channel MOSFET, rated at 40 V drain-source voltage and 9 A continuous drain current.

Key specifications

Parameter Value
Manufacturer PJSEMI
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 40 V 1
Gate-Source Voltage VGS -20 20 V 1
Drain Current-Continuous ID 9 A 1
Drain Current-Pulsed IDM 32 A Note1 1
Single Pulsed Avalanche Energy EAS 12.9 mJ Note4 1
Maximum Power Dissipation PD 2.5 W 1
Junction Temperature TJ 150 °C 1
Storage Temperature Range TSTG -55 150 °C 1
Drain-Source Breakdown Voltage V(BR)DSS 40 V VGS=0V,ID=250μA 2
Zero Gate Voltage Drain Current IDSS 1 μA VDS=40V,VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±20V,VDS=0V 2
Gate Threshold Voltage VGS(th) 1 1.65 2.5 V VDS=VGS,ID=250μA 2
Drain-Source On-Resistance RDS(on) 18 25 mΩ VGS=10V,ID=8A 2
Drain-Source On-Resistance RDS(on) 25 35 mΩ VGS=4.5V,ID=5A 2
Diode Forward Voltage VSD 1.2 V VGS=0V,IS=9A 2
Diode Forward Current IS 9 A 2
Forward Transconductance gFS 6.6 S VDS=5V,ID=2A 2
Input Capacitance Ciss 708 pF VDS=20V,VGS=0V,f=1MHz 2
Output Capacitance Coss 61 pF VDS=20V,VGS=0V,f=1MHz 2
Reverse Transfer Capacitance Crss 50 pF VDS=20V,VGS=0V,f=1MHz 2
Gate Resistance Rg 2 Ω VDS=0V,VGS=0V,f=1MHz 2
Total Gate Charge Qg 12 nC VDS=20V,ID=8A, VGS=10V 2
Gate-Source Charge Qgs 3.2 nC VDS=20V,ID=8A, VGS=10V 2
Gate-Drain Charge Qgd 3.1 nC VDS=20V,ID=8A, VGS=10V 2
Turn-on Delay Time td(on) 4 nS VDD=20V, RL=2.5Ω, VGS=10V,RGEN=3Ω 2
Turn-on Rise Time tr 3 nS VDD=20V, RL=2.5Ω, VGS=10V,RGEN=3Ω 2
Turn-off Delay Time td(off) 15 nS VDD=20V, RL=2.5Ω, VGS=10V,RGEN=3Ω 2
Turn-off Fall Time tf 2 nS VDD=20V, RL=2.5Ω, VGS=10V,RGEN=3Ω 2
Thermal Resistance, Junction-to-Ambient RθJA 50 °C/W Note2: surface mounted on FR4 board, t ≤ 10 sec 1

CAD (KiCad official)

  • Symbol: PJM09N40PA
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: pjm09n40pa-etched.step / pjm09n40pa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pjm09n40pa.step / pjm09n40pa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PJSEMI datasheet (7 pp, sha256 7945d23831b477ed, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF