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PJM05P30PA

PJSEMI · MOSFETs · SOP-8

PJM05P30PA from PJSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Source passive Source pin, one of three commonly tied source pins, with the device rated at a drain-source voltage of 30 V and gate-source voltage of ±20 V.
2 Source passive Source pin, one of three commonly tied source pins, with the device rated at a drain-source voltage of 30 V and gate-source voltage of ±20 V.
3 Source passive Source pin, one of three commonly tied source pins, with the device rated at a drain-source voltage of 30 V and gate-source voltage of ±20 V.
4 Gate input Gate pin, with gate-source voltage limited to ±20 V per the absolute maximum ratings.
5 Drain passive Drain pin, carrying continuous drain current up to 5.1 A with a drain-source voltage rating of 30 V.
6 Drain passive Drain pin, carrying continuous drain current up to 5.1 A with a drain-source voltage rating of 30 V.
7 Drain passive Drain pin, carrying continuous drain current up to 5.1 A with a drain-source voltage rating of 30 V.
8 Drain passive Drain pin, carrying continuous drain current up to 5.1 A with a drain-source voltage rating of 30 V.

Key specifications

Parameter Value
Manufacturer PJSEMI
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage -VDS 30 V 1
Gate-Source Voltage -VGS -20 20 V 1
Drain Current-Continuous -ID 5.1 A 1
Drain Current-Pulsed -IDM 20.4 A Repetitive rating, pulse width limited by maximum junction temperature (Note 1) 1
Maximum Power Dissipation PD 2.15 W 1
Junction Temperature TJ 150 °C 1
Storage Temperature Range TSTG -55 150 °C 1
Thermal Resistance, Junction-to-Ambient RθJA 58 °C/W Surface mounted on FR4 board, t ≤ 10 sec (Note 2) 1
Drain-Source Breakdown Voltage -V(BR)DSS 30 V VGS=0V,ID=-250μA 2
Zero Gate Voltage Drain Current -IDSS 1 μA VDS=-30V,VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±20V,VDS=0V 2
Gate Threshold Voltage -VGS(th) 1 1.5 2.5 V VDS=VGS,ID=-250μA 2
Drain-Source On-Resistance at VGS=-10V RDS(on) 43 55 mΩ VGS=-10V,ID=-5.1A 2
Drain-Source On-Resistance at VGS=-4.5V RDS(on) 65 90 mΩ VGS=-4.5V,ID=-4.2A 2
Forward Transconductance gFS 7.5 S VDS=-5V,ID=-4A 2
Input Capacitance Ciss 596 pF VDS=-15V, VGS=0V, f=1MHz 2
Output Capacitance Coss 95 pF VDS=-15V, VGS=0V, f=1MHz 2
Reverse Transfer Capacitance Crss 68 pF VDS=-15V, VGS=0V, f=1MHz 2
Turn-on Delay Time td(on) 14 nS VDD=-15V,VGS=-10V, ID=-1A, RGEN=2.5Ω 2
Turn-on Rise Time tr 61 nS VDD=-15V,VGS=-10V, ID=-1A, RGEN=2.5Ω 2
Turn-off Delay Time td(off) 19 nS VDD=-15V,VGS=-10V, ID=-1A, RGEN=2.5Ω 2
Turn-off Fall Time tf 10 nS VDD=-15V,VGS=-10V, ID=-1A, RGEN=2.5Ω 2
Total Gate Charge Qg 6.8 nC VDS=-15V,VGS=-10V, ID=-5.1A 2
Gate-Source Charge Qgs 1 nC VDS=-15V,VGS=-10V, ID=-5.1A 2
Gate-Drain Charge Qgd 1.4 nC VDS=-15V,VGS=-10V, ID=-5.1A 2
Diode Forward Voltage -VSD 0.8 1.2 V VGS=0V,IS=-5.1A 2
Diode Forward Current -IS 5.1 A 2

CAD (KiCad official)

  • Symbol: PJM05P30PA
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: pjm05p30pa-etched.step / pjm05p30pa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pjm05p30pa.step / pjm05p30pa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PJSEMI datasheet (5 pp, sha256 aa4bc3573302c190, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF