component
PJ9350L18SC
Public Made by Adomby adom
PJSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownPJ9350L18SC
PJSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3
PJ9350L18SC from PJSEMI, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the regulator (page 2 lists it as GND, Ground). |
| 2 | VOUT | power_out | Regulated output voltage; the fixed output is 1.8V for the PJ9350L18SC, and the datasheet recommends at least a 1uF capacitor from VOUT to ground for stability, with a maximum output current of 300mA. |
| 3 | VIN | power_in | Power input; the supply range is 2.5V to 6.5V, and VIN must stay at least the dropout voltage above VOUT for proper regulation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PJSEMI |
| Package | SOT-23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | ΔVOUT | -2 | 2 | % | VOUT ≥1.8V, IOUT=1mA | 8 | |
| Line Regulation | ΔVLINE | 0.01 | 0.15 | %/V | VIN=2.7~5.5V, IOUT=1mA | 8 | |
| Load Regulation | ΔVLOAD | 40 | 70 | mV | VOUT≤1.8V, IOUT=1~200mA | 8 | |
| Standby Current | IStandby | 1 | μA | VEN=0 | 8 | ||
| EN Logic High Voltage | VENH | 1.2 | V | VIN=5.5V, IOUT=1mA | 8 | ||
| EN Logic Low Voltage | VENlL | 0.4 | V | VIN=5.5V, VOUT=0V | 8 | ||
| EN Input Current | IEN | 1 | μA | VEN= 0~5.5V | 8 | ||
| Input Voltage | VIN | 2.5 | 6.5 | V | 8 | ||
| Supply Voltage | VIN | 2.5 | 6.5 | V | 7 | ||
| Maximum Output Current | 300 | mA | 7 | ||||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 7 | ||
| Maximum Input Voltage | VIN | -0.3 | 8 | V | 7 | ||
| Output Current | IOUT | 400 | mA | 7 | |||
| Power Dissipation | PD | 450 | mW | SOT-23-3 | 7 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 7 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 7 | ||
| Storage Temperature Range | TSTG | -55 | 150 | °C | 7 | ||
| ESD Voltage HBM | 2 | KV | HBM | 7 | |||
| Lead Temperature | 260 | °C | 10S | 7 | |||
| Thermal Resistance, Junction-to-Ambient | RθJA | 220 | °C/W | SOT-23-3 | 7 |
CAD (KiCad official)
- Symbol:
PJ9350L18SC - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3 (KiCad packages3D, STEP)
- 3D model files:
pj9350l18sc-etched.step/pj9350l18sc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pj9350l18sc.step/pj9350l18sc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PJSEMI datasheet (18 pp, sha256
07d6b42aa3d8f2df, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).