component

PJ75BL50SQ

Public Made by Adom

by adom

PJSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-89. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PJ75BL50SQ

PJSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89

PJ75BL50SQ from PJSEMI, in a SOT-89. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference pin; the input and output capacitors must return to this pin, and a wide copper trace is required for GND on the PCB.
2 VIN power_in Power input rated 3V to 36V in recommended operation (absolute maximum -0.3V to +40V), decoupled with a 1µF to 10µF ceramic capacitor placed as close to the device as possible.
3 VOUT power_out Regulated 5.0V output for this PJ75BL50SQ variant, supplying up to 200mA, with a 1µF to 10µF output capacitor (ESR 5mΩ to 100mΩ, X7R or X5R) placed close to OUT and GND.

Key specifications

Parameter Value
Manufacturer PJSEMI
Package SOT-89
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage VIN 3 36 V 6
Output Voltage Accuracy ΔVOUT -2 2 % IOUT=1mA 6
Quiescent Current IQ 2.5 4 μA IOUT=0mA 6
Dropout Voltage (VOUT=5.0V) VDROP 810 990 mV VOUT=5.0V, IOUT=150mA 6
Dropout Voltage (VOUT=5.0V) VDROP 510 600 mV VOUT=5.0V, IOUT=100mA 6
Line Regulation ΔVLINE 0.2 %/V VIN=VOUT+2V to 30V, IOUT=10mA 6
Load Regulation ΔVLOAD 5 20 mV VIN=VOUT+2V, 1mA<IOUT<150mA 6
Supply Voltage (recommended) 3 36 V 5
Maximum Output Current (recommended) 200 mA 5
Operating Ambient Temperature TA -40 125 °C 5
Supply Voltage (absolute maximum) -0.3 40 V 5
Power Dissipation SOT-89 PD 600 mW SOT-89 package 5
Thermal Resistance, Junction-to-Ambient SOT-89 180 °C/W SOT-89 package 5
Operating Junction Temperature TJ -40 125 °C 5
Storage Temperature Range TSTG -65 150 °C 5
Lead Temperature (Soldering) 300 °C 10 sec soldering 5
ESD Voltage -4000 4000 V HBM 5
Short Current Protection IShort 100 mA OUT short to GND 6
Output Noise eN 120 μVRMS 10Hz to 100KHz, IOUT=30mA 6
Power Supply Rejection Ratio PSRR 68 dB VIN=12V, IOUT=1mA, f=1KHz 6
Maximum Output Current IOUT(Max) 200 mA 6

CAD (KiCad official)

  • Symbol: PJ75BL50SQ
  • Footprint: Package_TO_SOT_SMD:SOT-89-3
  • 3D model: SOT-89 (KiCad packages3D, STEP)
  • 3D model files: pj75bl50sq-etched.step / pj75bl50sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pj75bl50sq.step / pj75bl50sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PJSEMI datasheet (14 pp, sha256 d9ee3992109c7815, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF