# PJ75AL33SQ

**PJSEMI** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3

PJ75AL33SQ from PJSEMI, in a SOT-89-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin, to be connected as a single point ground with short, wide traces for the input and output capacitor returns. |
| 2 | VIN | power_in | Power input pin, rated for input voltages up to 36 V (supply voltage absolute maximum -0.3 to +36 V), with a 10 µF ceramic input capacitor placed as close to the device as possible. |
| 3 | VOUT | power_out | Regulated output pin, with output current of 100 mA typical (70 mA minimum at VIN = VOUT + 2 V) and a required 10 µF ceramic output capacitor (X7R or X5R) placed close to VOUT and GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | PJSEMI |
| Package | SOT-89-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | ΔVOUT | -2 |  | 2 | % | IOUT=10mA | 4 |
| Output Current | IOUT | 70 | 100 |  | mA | VIN=VOUT+2V | 4 |
| Quiescent Current | IQ |  | 2.5 | 3 | μA | IOUT=0mA | 4 |
| Dropout Voltage (3.0V<VOUT≤5.0V row, applies to 3.3V) | VDROP |  | 25 | 55 | mV | 3.0V<VOUT≤5.0V, IOUT=1mA | 4 |
| Line Regulation | ΔVLINE |  |  | 0.2 | %/V | VIN=VOUT+2 to 30V,IOUT=1mA | 4 |
| Load Regulation | ΔVLOAD |  | 25 | 60 | mV | VIN=VOUT+2V,1mA<IOUT<50mA | 4 |
| Thermal Shutdown Temperature (row label as printed) | ∆VOUT/VOUT ×∆TA |  | 100 |  | °C | VIN=VOUT+2V,IOUT=10mA -40°C≤TA≤85°C | 4 |
| Input Voltage | VIN |  |  | 36 | V |  | 4 |
| Supply Voltage | VIN | -0.3 |  | 36 | V |  | 3 |
| Power Dissipation (SOT-89) | PD |  |  | 600 | mW |  | 3 |
| Storage Temperature Range | TSTG | -50 |  | 125 | °C |  | 3 |
| Operating Ambient Temperature | TA | -40 |  | 85 | °C |  | 3 |
| Thermal Resistance, Junction-to-Ambient (SOT-89) | RθJA |  |  | 180 | °C/W |  | 3 |
| Maximum Operating Junction Temperature | TJ(MAX) |  |  | 125 | °C |  | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | must be back to the PJ75A Series ground pin using as wide and as short of a copper trace as is | 5 |

## CAD (KiCad official)

- Symbol: `PJ75AL33SQ`
- Footprint: `Package_TO_SOT_SMD:SOT-89-3`
- 3D model: SOT-89-3 (KiCad packages3D, STEP)
- 3D model files: `pj75al33sq-etched.step` / `pj75al33sq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pj75al33sq.step` / `pj75al33sq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [PJSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911959563776000) (9 pp, sha256 `ec9ac50694a28a8f`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pj75al33sq-datasheet.pdf)